T9000
Preliminary Data Sheet
November 2000
ISDN Network Termination Node (NTN) Device
Figure 10 shows the structure of the status byte. Each
bit is set to one when the corresponding condition is
active.
9 HDLC with FIFO Module (continued)
9.3 HDLC Receiver
Bit 7 (OVR). The overrun bit indicates that the frame
has been closed by a receive FIFO overrun condition
(see section 9.3.1.1 Overrun Condition ).
Downstream D channel is always transferred to the
HDLC receiver. The HDLC receiver removes flags,
does zero bit deletion, and calculates the FCS for the
downstream D-channel information. Deframed data is
converted from serial to parallel (byte delimited) and
passed to the microcontroller through the receiver
FIFO HRX register.
Bit 6 (EOF). The end of frame bit indicates that the
packet has been properly terminated with a closing
flag.
Bit 5 (FERR). The FCS error bit indicates that the
results of comparing the incoming FCS with internally
calculated FCS on the received data (according to the
ITU CRC-16 polynomial) did not match.
9.3.1 HDLC Receiver Initialization
On powerup, the HDLC receiver is initialized automati-
cally. After powerup, whenever there is any change to
the HRCF[DROPCRC], HRCF[RXMODE],
HRCF[BAE], or HSM0[BAP(7:0)] configuration bits, the
bit HRCF[RX_INIT] must be set to 1 to reinitialize the
HDLC receiver. Once the initialization is completed, the
HRCF[RX_INIT] bit automatically returns to 0.
Bit 4 (FABRT). The frame abort bit indicates that the
frame has been closed with an abort pattern
(01111111).
Bits 2—0 (CBIT). The check error bit provides an extra
error check. In most HDLC based protocols, the packet
length is an exact multiple number of bytes. When this
is the case, CBIT = 111. Otherwise, CBIT ≠ 111.
During initialization, register bit HRCF[DROPCRC] is
sampled. If it is one (the default), the FCS will be
dropped (not stored in the receiver FIFO). If
HRCF[DROPCRC] = 0, the complete deframed packet,
including its FCS, will be stored in the receiver FIFO.
The above definitions for the status bits imply that cor-
rectly received frames will have 47h as the status byte.
Bit 3 is reserved and is set to 0.
7
6
5
4
3
2:0
If the device is programmed for address matching, then
prior to storing a packet in the receiver FIFO, its
address is checked against a set of patterns (see Sec-
tion 9.4, Address Recognition). Only packets with an
address field matching one of the programmed
OVR
EOF
FERR FABRT
—
CBIT
Figure 10. HDLC Receiver Status Word
address values are transferred to the receiver FIFO, all
others are rejected. At the end of a frame, a status byte
is transferred to the HDLC receiver FIFO that provides
information about the following events: frame-overrun,
frame-complete, frame-error, and frame-abort.
Multiple packets may be stored in the receiver FIFO at
a given time. The HRDA[NBNSW] register bits indicate
the number of bytes until the next status word in the
FIFO. If there are no status words in the FIFO, it indi-
cates the number of bytes of an unfinished packet cur-
rently stored into the FIFO.
Packets less than 2 bytes in length (4 bytes if
HRCF[DROPCRC] = 1) are automatically rejected.
54
Lucent Technologies Inc.
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