T9000
Preliminary Data Sheet
November 2000
ISDN Network Termination Node (NTN) Device
9.1.1 HDLC Transmitter Initialization
9 HDLC with FIFO Module
On powerup, the HDLC transmitter is initialized auto-
matically. After powerup, whenever there is any change
to the HTCF[MANCRC] or HTCF[TXMODE] configura-
tion bits, the bit HTCF[TX_INIT] needs to be set to 1 to
reinitialize the HDLC transmitter. Once the initialization
is completed, the HTCF[TX_INIT] bit returns to 0.
The HDLC (high-level data link) module supports stan-
dard HDLC framing and deframing functionality on the
D channel of the NTN. Two 64 x 9 register files are
used to implement transmitter and receiver FIFOs, and
address recognition is performed on the incoming
frames.
During initialization, register bit HTCF[MANCRC] is
sampled. If it is zero (the default), the FCS will be cal-
culated automatically, according to the ITU 16 polyno-
mial cyclic redundancy check (CRC-16) and inserted at
the end of the user data. If HTCF[MANCRC] = 1, no
FCS automatic insertion is done; it is the responsibility
of the user software to perform the FCS insertion if
desired. This feature may be useful in cases where it is
necessary to use an FCS other than that in the ITU
standard.
Data/parameter exchange between the microcontroller
and the HDLC module is done by reading/writing a set
of registers. Interrupts are used to request microcon-
troller intervention.
Data to be framed and transmitted is written into the
FIFO by the microcontroller via registers HTX and
HTXL. All bytes of a packet, except the last one, are
written to HTX. The last byte is written to HTXL. HTX
and HTXL occupy the same physical space (the trans-
mit FIFO).
Users may abort the current frame transmission by
asserting register bit HTCF[ABRT_RQ]. When this
occurs, the transmitter FIFO manager will flush the
contents of the transmitter FIFO. This bit automatically
returns to 0 once the abort sequence has been initi-
ated.
The microcontroller reads data from the receive FIFO
via register HRX.
9.1 HDLC Transmitter
Register bit HTCF[IDL] determines the idle pattern to
be sent by the HDLC transmitter when there are no
packets to be framed. If set to 0, flags (01111110) will
be inserted between the closing flag of a frame and the
opening flag of the next frame. If set to 1, idles
(11111111) will be inserted.
The HDLC transmitter automatically frames user data
packets (UDPs) by inserting starting and closing flags,
inserting (if requested) the frame check sequence (cal-
culated according to the ITU-16 polynomial cyclic
redundancy check [CRC]) and performing zero-bit
insertion on the user data and frame check sequence
(FCS).
In certain applications where buffer overloading at the
far-end receiver can occur, there may be a requirement
to add a minimum number of extra interframe fill bytes
at the end of each frame. HTCF[FCNT(2:0)] deter-
mines the number of fill bytes to be sent at the end of a
packet. For FCNT(2:0) = n (where n > 0), n – 1 inter-
frame flags are padded after the closing flag of one
frame and the opening flag of the next frame. For the
case of n = 0, the closing flag of one frame acts as the
opening flag of the next frame (i.e., back-to-back
frames are supported).
Packets to be framed are transferred by the microcon-
troller into the transmitter FIFO by writing to the HTX
and HTXL registers. Multiple HDLC packets can be
written into the transmitter FIFO. For all bytes of a
packet, except the last one, the microcontroller should
write the data byte into the HTX register. The last byte
of a packet is written into the HTXL register. Figure 9
shows the transmitter FIFO contents in the case where
the microcontroller has written two complete 9-byte
packets into the transmitter FIFO and partially written a
third packet. For packets #1 and #2, bytes 0 to 7 are
written to register HTX and byte 8 is written to register
HTXL. The HDLC transmitter FIFO manager indicates
the number of free bytes currently in the transmitter
FIFO via read-only register HTSA. At the snapshot in
time represented by the figure, the HDLC transmitter is
ready to accept byte P3-B2. Also, the microcontroller
can write up to 48 bytes before the FIFO is filled,
because the first four bytes of the first packet have
been transmitted.
The HTTH[TFAE] register bits determine the threshold
that the queue manager uses to control assertion of the
HIR[TTHR] interrupt register bit. This bit is asserted
when, as a consequence of a read of the transmitter
FIFO by the HDLC framer, the available space of the
FIFO exceeds the number in the HTTH[TFAE].
Interrupt register bit HIR[TFC] is asserted at the end of
the closing flag of a transmitted frame.
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