T9000
Preliminary Data Sheet
November 2000
ISDN Network Termination Node (NTN) Device
9.2 HDLC Transmitter D-Channel Access
9 HDLC with FIFO Module (continued)
The HDLC transmitter accesses the upstream D chan-
nel using a priority mechanism (implemented via an
arbitration circuit) equivalent to that specified in the
ITU-I.430 standard for TEs on the S/T bus. The arbiter
automatically grants control to the HDLC module if one
of these conditions occurs:
9.1 HDLC Transmitter (continued)
9.1.1 HDLC Transmitter Initialization (continued)
Interrupt register bit HIR[TUNDR] is asserted to indi-
cate that an underrun error has occurred during the
transmission of a frame. An underrun error occurs
when the transmitter has completed the transmission
of a user byte that is not the last of a packet and
detects that the transmitter FIFO is empty. In this case,
the frame is completed by inserting the abort pattern,
01111111.
■ S/T-interface is not fully active (no INFO 3 is being
received on the S/T-interface).
■ SCR0[FACT] register bit is set to 1.
■ DFR[FORCE_D] register bit is set to 1.
When none of the above conditions are true and INFO
3 is being received on the S/T-interface, the priority cir-
cuit determines when the HDLC module is granted
access to the upstream D channel. The arbiter will
grant access to the HDLC module when 8 or 9 (for pri-
ority class 1) or 10 or 11 (for priority class 2) consecu-
tive ones are received on the upstream S/T D channel.
The priority class is controlled via register bit
HTTH[PCLASS]. Within a priority class, the priority
level (i.e., 8/9 or 10/11) is automatically managed.
Once the packet has been transmitted, the HDLC mod-
ule releases control to the internal arbiter for a new
arbitration.
P3-B1 (TEI)
P3-B0 (SAPI)
P2-LASTBYTE
P2-B7
P2-B6
P2-B5
P2-B4
P2-B3
P2-B2
UDP #2
P2-B1 (TEI)
P2-B0 (SAPI)
P1-LASTBYTE
P1-B7
When the S/T-interface is active, the microcontroller
may force access to the upstream D channel to be
granted to the HDLC module by asserting register bit
DFR[FORCE_D]. Normally, the upstream (received) D-
channel bit (D bit) from the TEs is echoed downstream
in the E-bit position. When FORCE_D is asserted, the
inverted version of the D bit is echoed. This has the
effect of guaranteeing that all active TEs will cease
transmission (due to a collision error) and no new
transmissions will be initiated. In this way, upstream
access to the D channel is granted exclusively to the
local HDLC controller.
P1-B6
P1-B5
P1-B4
P1-B3
UDP #1
P1-B2
PI-B1 (TEI)
P1-B0 (SAPI)
WPTR = 14h
RPTR = 04h
HTSA = 30h
5-7099F
Note: RPTR = read pointer, WPTR = write pointer.
Figure 9. HDLC Transmitter FIFO
When the S/T-interface is disabled (SCR0[ST_E] = 0)
or in force activate mode (SCR0[FACT] = 1), the HDLC
transmitter will be granted immediate access to the
upstream D channel. If the HDLC module is granted
access to the D channel and does not have any data to
transmit, it will transmit the idle pattern determined by
HTCF[IDL]. For operation with TEs running the LAPD
protocol, HTCF[IDL] should be set to 1.
Lucent Technologies Inc.
53
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