T9000
Preliminary Data Sheet
November 2000
ISDN Network Termination Node (NTN) Device
7 Transmission Superblock (continued)
7.6 DFAC Register Set (continued)
Table 37. UIR: U-Interface Interrupt Register (0x14)
Reg
R/W
Bit 7
RSF
0
Bit 6
RHSF
0
Bit 5
BERR
0
Bit 4
ACTSC
0
Bit 3
OUSC
0
Bit 2
Bit 1
Bit 0
ECNFY
0
UIR
R
EOC3SC EOCSC
RESET Default
0
0
Note: All bits in this register are set to 1 upon occurrence of the corresponding interrupt condition, and are cleared
to 0 when the register is read.
Bit #
Symbol
Name/Description
Receive Superframe. This interrupt occurs at the beginning of each downstream U-inter-
face superframe, and signifies that a new group of U-overhead bits is available.
7
RSF
Receive Half Superframe. This interrupt occurs just after processing the downstream EOC
data/message on the U-interface, i.e., every half superframe (6 ms). This can be useful in
the case of any nonstandard use of the EOC channel where it is required to know when new
data has arrived. If a response to the incoming EOC message is required (for example, in
the case of manual EOC processing), the microcontroller has approximately 1.5 ms to write
the response data to registers ECR0 and ECR1 before it is transmitted.
6
RHSF
Block Error. This interrupt occurs on U-superframe boundaries whenever a NEBE or FEBE
error has been detected in the previous superframe. The most recent NEBE and FEBE val-
ues are available in register USR0.
5
4
BERR
Downstream Activation State Change. This interrupt occurs whenever any of the follow-
ing bits (found in register USR0) change state: ACTDN, XACT, OOF_n, DEA_n, UOA_n,
AIB_n.
ACTSC
Other U-Interface State Change. This interrupt occurs whenever any of the following bits
(found in register USR1) change state: R15R, R16R, R25R, R34R, R44R, R54R, R64R.
3
2
OUSC
New Trinal-Checked EOC Message Received. This interrupt occurs when a trinal-
checked EOC message has been received that is different than the most recent trinal-
checked EOC message.
EOC3SC
New EOC Message Received. This interrupt occurs whenever the current EOC message
is different from the previous EOC message (no trinal-checking is performed).
1
0
EOCSC
ECNFY
EOC Corrupt CRC Notify State Change. This is a status bit only. It will not cause an inter-
rupt (so it has no corresponding enable bit in register UIE); it is for polling only. It is only valid
when in AUTOEOC mode. It provides a way to monitor the current output of the EOCSM,
and is logically part of the group of bits ECCRC, ELBK2, ELB2, ELB1 found in ESR0.
44
Lucent Technologies Inc.
AGERE [ AGERE SYSTEMS ]
