T9000
Preliminary Data Sheet
November 2000
ISDN Network Termination Node (NTN) Device
7 Transmission Superblock (continued)
7.6 DFAC Register Set (continued)
Table 32. SCR0: S-Interface Control Register #0 (0x0F)
Reg
SCR0
RESET
R/W
R/W
Bit 7
—
Bit 6
—
Bit 5
STOA
0
Bit 4
FACT
0
Bit 3
FT
0
Bit 2
MF_E
0
Bit 1
ST_E
1
Bit 0
SRESET
0
Default
0
0
Bit #
7—6
5
Symbol
Name/Description
—
Reserved. Program to 0.
S/T-Only Activation. This bit allows the S/T-interface to perform a normal activation independent of the
state of the U-interface. The S block will behave as if synchronization has been achieved on the U-inter-
face and the downstream U-interface ACT bit has been received. It will reach its full activation state (G3,
transmitting INFO4) only if a TE is attached. Note the difference in function between this bit and FACT,
below.
STOA
0: Normal operation.
1: Allows S/T activation independent of the U-interface state.
When STOA is cleared to zero, the SRESET bit must be asserted. If a U-interface activation occurs
while STOA is active, STOA must be deasserted before any further U-activation attempts will be recog-
nized by the device.
S/T Force Activation. This bit forces the S/T-interface to proceed directly to its full activation state (G3,
transmitting INFO4) regardless of whether a TE is attached or what the state of the U-interface is. This
may be useful for test purposes. Note the difference in function between this bit and STOA, above. In
order for this bit to have any effect, the S/T-interface must be enabled.
4
FACT
0: Normal operation.
1: Forces S block to transmit INFO4.
If a U-interface activation occurs while FACT is active, FACT must be deasserted before any further U-
activation attempts will be recognized by the device.
Fixed/Adaptive Timing Selection. Determines whether the S/T-interface receiver uses fixed or adap-
tive timing.
3
FT
0: Adaptive timing. When this bit is set to 0, incoming data at the S/T-interface is sampled at a point
defined by an adaptive timing algorithm. This mode is used in point-to-point configuration (only 1
TE) or a multi-TE configuration on an extended passive bus, where the round-trip delay can vary
from 10 µs to 42 µs, but the differential delay between various TEs is less than 2 µs.
1: Fixed timing. When this bit is set to 1, incoming data at the S/T-interface is sampled with a fixed
delay relative to the S/T transmitter clock. This mode is used in a multi-TE configuration with a
short passive bus, where the round-trip delay variations are 10 µs to 14 µs.
S/T-Interface Multiframing Enable. Enables the multiframing controller and allows the microcontroller
to access the S and Q channels. When disabled, multiframing is not implemented (the device transmits
all 0s in the FA and M bit positions and all 1s in the S bit positions to the TE). Also register bits
MFR0(3:0) are forced to 1 and MFR1(3:0) are forced to 0 when multiframing is disabled.
2
MF_E
0: Disable multiframing controller.
1: Enable multiframing controller.
S/T-Interface Enable. This signal enables the S/T-interface.
1
0
ST_E
0: S/T-interface is powered down and disabled.
1: S/T-interface is enabled and can respond to activation attempts.
S/T-Interface Reset. Writing a one to this bit causes a reset of the S/T-interface, initializing the interface
in the same manner as the external RESET pin.
SRESET
0: Normal operation.
1: Reset S/T-interface (nonlatching—this bit clears itself and will always be read back as 0).
40
Lucent Technologies Inc.
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