T9000
Preliminary Data Sheet
November 2000
ISDN Network Termination Node (NTN) Device
7 Transmission Superblock (continued)
7.6 DFAC Register Set (continued)
Table 35. MFR0: Multiframe Register, Q-Channel Data (0x12)
Reg
R/W
Bit 7
—
Bit 6
—
Bit 5
—
Bit 4
—
Bit 3
QD1
1
Bit 2
QD2
1
Bit 1
QD3
1
Bit 0
QD4
1
MFR0
R
RESET Default
—
—
—
—
Bit #
7—4
3—0
Symbol
Name/Description
—
Reserved.
Q-Channel Data. When multiframing is enabled (SCR0[MF_E] = 1), these bits contain the
Q-channel bits of the most recent complete multiframe. When multiframing is disabled, these
bits are set to 1. The interrupt bit SIR0[QSC] can be used to notify the microcontroller of the
reception of a new Q-channel message. In order to avoid having the existing Q-channel data
overwritten by a new Q-channel message, the read operation must be complete within 20
S/T-interface frames of when QSC becomes asserted, that is 5 ms. The order of transmission
is Q1 first to Q4 last.
QD[1:4]
Table 36. MFR1: Multiframe Register, S-Subchannel Data (0x13)
Reg
R/W
Bit 7
—
Bit 6
—
Bit 5
—
Bit 4
—
Bit 3
SSD1
0
Bit 2
SSD2
0
Bit 1
SSD3
0
Bit 0
SSD4
0
MFR1
W
RESET Default
0
0
0
0
Bit #
Symbol
Name/Description
—
Reserved. Program to 0.
7—4
S-Subchannel Data, Subchannels 1 to 5. When multiframing is enabled (SCR0[MF_E] = 1),
these bits can be written to transmit data onto the five S subchannels SC1—SC5. When mul-
tiframing is disabled, these bits are set to 0. The interrupt bit SIR[SSRDY] can be used to
notify the microcontroller that this register is ready to accept a new set of S-subchannel data.
Up to 5 nibbles may be written to this register upon reception of the SSRDY interrupt. Each
successive nibble written will be transmitted on the next available subchannel, and if less
than 5 nibbles are written, the remaining subchannels will transmit all 1s. For example, if two
nibbles are written, the first nibble will be transmitted on subchannel SC1, the second nibble
will be transmitted on subchannel SC2, and all 1s will be transmitted on the remaining sub-
channels, SC3—SC5. The write operation must be complete within five S/T-interface frames
of when SSRDY becomes asserted (1.25 ms). The order of transmission is SSD1 first to
SSD4 last.
3—0 SSD[1:4]
Lucent Technologies Inc.
43
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