Advisory
November 1999, Rev. 4
Exceptions and Clarifications for AmbassadorTM T8100A, T8102,
and T8105 H.100/H.110 Interface and Time-Slot Interchangers
Root Cause: The analog PLL has an error which
introduces an unexpected 6 ns—7 ns of skew.
Device Exceptions
This skew causes the phase alignment circuit to
Users of the Ambassador T8100A, T8102, and
fail intermittently, whether in the SNAP or SLIDE
T8105 devices should be aware of the following
mode. An intermittent SLIDE produces an internal
device operation exceptions and the associated solu-
frame signal that does not align and phase lock
tions:
with an incoming frame reference. An intermittent
1. When a compatibility clock is programmed as a
SNAP forces a reset of the internal counters and
slave, and the board generates A or B clocks, the
results in corrupted stream data.
watchdog will indicate an error on the A or B
clocks it generates. The error will be reported
Workaround: There is no workaround. The solu-
tion is a fix to the silicon. Samples are scheduled
even though the generated clocks are good.
for release in August 1999.
Workaround: Use the master board to accurately
4. Version 2 models of the Ambassador T8100A,
monitor the clocks.
T8102, and T8105 devices can exhibit intermittent
2. When a compatibility clock is programmed as a
corrupted time slot data in one specific configura-
slave, and the clock selector is set to A or B
tion. The problem occurs when a master T810x
clocks with slide phase alignment, the slave board
device is given an 8 kHz signal as the timing
does not lock and the generated frame continues
reference and multiplies it up to 2.048 MHz or
sliding.
4.096 MHz in the digital PLL (DPLL). The DPLL
introduces sufficient jitter on the A or B master
output clocks that slave devices falsely interpret
as a loss of sync and either snap or slide align to
Workaround: None.
Product Status: Device redesign required.
this false sync indication. This, in turn, causes
3. Models of the Ambassador T8100A, T8102, and
corruption of time slot data. Any master timing ref-
T8105 devices exhibit intermittent corrupted time-
erence that does not make use of the DPLL does
slot data. H.100 stream 0 time slot 1 (for outgoing
data) and H.100 stream 1 time slot 127 (for
not exhibit the problem.
incoming data at 8.192 MHz, time slot 63 for
Workaround: Do not use an 8 kHz signal as the A
4.096 MHz, and time slot 31 for 2.048 MHz) are
or B master timing reference, since this requires
the most likely stream/time slots to be corrupted.
use of the DPLL. Instead, supply a jitter-free tim-
However, intermittent time-slot corruption may
ing reference at any of the other allowable fre-
occur in other stream/time slots.
quencies (2.048, 4.096, 8.192 or 16.384 MHz).
The time-slot corruption problem occurs when a
T810x device is used in slave-timing mode, as
Product Status: The solution is a fix to the
silicon.
described in Section 2.5 of the Data Sheet. In a
typical slave timing application, a T810x device is
set to phase align to an incoming bitclock/frame
reference pair (i.e., slave to CT_C8_A/FRAME_A,
CT_C8_B/FRAME_B, C4/FR_COMP, etc.). Both
SNAP and SLIDE alignment modes are affected.
Devices that don't require phase alignment to
these clocks (i.e., the primary bus master) should
not exhibit stream data corruption.
AGERE [ AGERE SYSTEMS ]
