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T8102A 参数 Datasheet PDF下载

T8102A图片预览
型号: T8102A
PDF下载: 下载PDF文件 查看货源
内容描述: H.100 / H.110接口和时隙交换 [H.100/H.110 Interface and Time-Slot Interchangers]
分类和应用:
文件页数/大小: 112 页 / 1382 K
品牌: AGERE [ AGERE SYSTEMS ]
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Ambassador T8100A, T8102, and T8105  
H.100/H.110 Interfaces and Time-Slot Interchangers  
Advance Data Sheet  
November 1999  
There is only one combination which forms a TSof  
+127 or –127:  
Appendix B. Minimum Delay and  
Constant Delay Connections  
TS= TS(127) – TS(0) = +127, and  
TS= TS(0) – TS(127) = –127,  
B.1 Connection Definitions  
but there are two combinations which form TSs of  
+126 or –126:  
Forward  
Connection  
A forward connection is defined as one  
in which the output (to) time slot has a  
greater value than the input (from) time  
slot, or put another way, the delta  
between them is positive.  
A reverse connection is defined as one  
in which the output (to) time slot has a  
lesser value than the input (from) time  
slot, and the delta between them is  
negative.  
TS= TS(127) – TS(1) = TS(126) – TS(0) = +126, and  
TS= TS(1) – TS(127) = TS(0) – TS(126) = –126,  
there are three combinations which yield +125 or –125,  
and so on.  
Reverse  
Connection  
The user can utilize the TSto control the latency of  
the resulting connection. In some cases, the latency  
must be minimized. In other cases, such as a block of  
connections which must maintain some relative integ-  
rity while crossing a frame boundary, the required  
latency of some of the connections may exceed one  
frame (>128 time slots) to maintain the integrity of this  
virtual frame.  
So, for example, going from TS(1) to TS(38) is a for-  
ward connection, and the TSis +37, but going from  
TS(38) to TS(1) is a reverse connection, with a TSof  
–37:  
where TS= TS(to) – TS(from).  
Each device contains several bits for controlling  
latency. Each connection has a bit which is used for  
selecting one of two alternating data buffers. These bits  
are set in the local connection memory (T8100A,  
T8105 only) for local switching or in the tag register  
field of the CAM section for H-bus switching. There are  
also 2 bits in the CON register, address 0x0E, which  
can control the buffer selection on a chip-wide basis.  
Bit 1 of the register overrides the indiv idual FME bits.  
Bit 0 becomes the global, chip-wide, FME setting.  
Similarly, a delta can be introduced for streams which  
will have a bearing in certain exceptions (discussed  
later):  
STR= STR(to) – STR(from)  
Lucent Technologies Inc.  
103  
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