Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Timing Characteristics (continued)
Clock Timing
.
Table 52 ExpressCLK (ECLK) and Fast Clock (FCLK) Timing Characteristics
<
<
<
<
T +85 °C.
DD
A
DD
A
OR3Cxx Commercial: V
= 5.0 V ± 5%, 0 °C
T
70 °C; Industrial: V
= 5.0 V ± 10%, –40 °C
DD = 3.0 V to 3.6 V, 0 °C < TA < 70 °C; Industrial: VDD = 3.0 V to 3.6 V, –40 °C < TA < +85 °C.
OR3Txxx Commercial: V
Speed
Device
Symbol
Unit
-4
-5
-6
-7
J
DD
(T = 85 °C, V = min)
Min Max Min Max Min Max Min Max
ECLKC_DEL
ECLKM_DEL
Clock Control Timing Delay Through
CLKCNTRL (input from corner)
0.31
1.54
—
—
0.31
1.17
—
—
0.31
1.00
—
—
0.31
0.92
—
—
ns
ns
Delay Through CLKCNTRL (input from inter-
nal clock controller PAD)
Clock Shutoff Timing:
OFFM_SET
OFFM_HLD
OFFC_SET
OFFC_HLD
ECLKM_DEL
Setup from Middle ECLK (shut off to CLK)
Hold from Middle ECLK (shut off from CLK)
Setup from Corner ECLK (shut off to CLK)
Hold from Corner ECLK (shut off from CLK)
0.77
0.00
0.77
0.00
—
—
—
—
0.51
0.00
0.51
0.00
—
—
—
—
0.44
0.00
0.44
0.00
—
—
—
—
0.41
0.00
0.41
0.00
—
—
—
—
ns
ns
ns
ns
ECLK Delay (middle pad):
OR3T20
—
—
—
—
—
—
—
3.50
3.67
—
—
—
—
—
—
2.56
2.62
2.74
2.86
3.06
—
—
—
—
—
2.05
2.08
2.13
2.19
2.29
—
—
—
—
—
1.78
1.80
1.85
1.90
1.98
ns
ns
ns
ns
ns
OR3T30
OR3C/T55
OR3C/T80
OR3T125
ECLKC_DEL
FCLKM_DEL
FCLKC_DEL
ECLK Delay (corner pad):
OR3T20
OR3T30
OR3C/T55
OR3C/T80
—
—
—
—
—
—
—
5.47
5.64
—
—
—
—
—
—
4.48
4.53
4.64
4.77
4.96
—
—
—
—
—
3.85
3.97
4.22
4.47
4.85
—
—
—
—
—
3.36
3.47
3.69
3.92
4.27
ns
ns
ns
ns
ns
OR3T125
FCLK Delay (middle pad):
OR3T20
OR3T30
OR3C/T55
OR3C/T80
—
—
—
—
—
—
—
8.24
8.87
—
—
—
—
—
—
5.91
6.12
6.59
7.11
7.98
—
—
—
—
—
4.59
4.66
4.83
5.01
5.33
—
—
—
—
—
3.81
3.89
4.06
4.26
4.59
ns
ns
ns
ns
ns
OR3T125
FCLK Delay (corner pad):
OR3T20
OR3T30
OR3C/T55
OR3C/T80
—
—
—
—
—
—
—
10.34
11.01
—
—
—
—
—
—
7.88
8.11
8.60
9.15
10.07
—
—
—
—
—
6.41
6.58
6.95
7.34
7.96
—
—
—
—
—
5.40
5.58
5.94
6.33
6.94
ns
ns
ns
ns
ns
OR3T125
Notes:
The ECLK delays are to all of the PICs on one side of the device for middle pin input, or two sides of the device for corner pin input. The delay
includes both the input buffer delay and the clock routing to the PIC clock input.
The FCLK delays are for a fully routed clock tree that uses the ExpressCLK input into the fast clock network. It includes both the input buffer
delay and the clock routing to the PFU CLK input. The delay will be reduced if any of the clock branches are not used.
Lucent Technologies Inc.
123
AGERE [ AGERE SYSTEMS ]
