Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Timing Characteristics (continued)
.
Table 55 OR3Cxx Fast Clock (FCLK) to Output Delay (Pin-to-Pin)
<
<
<
<
<
DD
A
DD
A
L
OR3Cxx Commercial: V
= 5.0 V ± 5%, 0 °C
= 3.0 V to 3.6 V, 0 °C
T
70 °C; Industrial: V
= 5.0 V ± 10%, –40 °C
DD
T
+85 °C; C = 50 pF.
<
<
<
DD
A
A
T
OR3Txxx Commercial: V
T
70 °C; Industrial: V
= 3.0 V to 3.6 V, –40 °C
+85 °C;
L =
C
50 pF.
Speed
Description
Device
Unit
-4
-5
-6
-7
J
DD
(T = 85 °C, V = min)
Min
Max
Min
Max
Min
Max
Min
Max
Output Not on Same Side of Device As Input Clock (Fast Clock Delays Using ExpressCLK Inputs)
→
ECLK Middle Input Pin OUTPUT Pin
(Fast)
OR3T20
OR3T30
OR3C/T55
OR3C/T80
OR3T125
—
—
—
—
—
—
—
14.68
15.30
—
—
—
—
—
—
11.13
11.35
11.81
12.33
13.20
—
—
—
—
—
7.94
8.01
8.18
8.36
8.68
—
—
—
—
—
6.40
6.48
6.66
6.85
7.19
ns
ns
ns
ns
ns
→
ECLK Middle Input Pin OUTPUT Pin
(Slewlim)
OR3T20
OR3T30
OR3C/T55
OR3C/T80
OR3T125
—
—
—
—
—
—
—
17.11
17.74
—
—
—
—
—
—
13.12
13.33
13.80
14.32
15.19
—
—
—
—
—
8.61
8.68
8.85
9.04
9.35
—
—
—
—
—
6.93
7.01
7.19
7.38
7.72
ns
ns
ns
ns
ns
→
ECLK Middle Input Pin OUTPUT Pin
(Sinklim)
OR3T20
OR3T30
OR3C/T55
OR3C/T80
OR3T125
—
—
—
—
—
—
—
18.47
19.10
—
—
—
—
—
—
14.47
14.68
15.15
15.67
16.54
—
—
—
—
—
13.46
13.53
13.70
13.88
14.20
—
—
—
—
—
11.67 ns
11.75 ns
11.93 ns
12.12 ns
12.46 ns
Additional Delay if ECLK Corner Pin
Used
OR3T20
OR3T30
OR3C/T55
OR3C/T80
OR3T125
—
—
—
—
—
—
—
2.10
2.14
—
—
—
—
—
—
1.97
1.99
2.01
2.04
2.09
—
—
—
—
—
1.82
1.92
2.12
2.33
2.63
—
—
—
—
—
1.60
1.69
1.88
2.07
2.39
ns
ns
ns
ns
ns
Notes:
Timing is without the use of the programmable clock manager (PCM).
This clock delay is for a fully routed clock tree that uses the primary clock network. It includes both the input buffer delay, the clock routing to the
→
PIO CLK input, the clock Q of the FF, and the delay through the output buffer. The delay will be reduced if any of the clock branches are not
used. The given timing requires that the input clock pin be located at one of the six ExpressCLK inputs of the device and that a PIO FF be used.
PIO FF
D
Q
OUTPUT (50 pF LOAD)
CLKCNTRL
FCLK
ECLK
5-4846(F).b
Figure 77. Fast Clock to Output Delay
126
Lucent Technologies Inc.
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