Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Timing Characteristics (continued)
CS_SET
A_HLD
A_SET
ADSN_HLD
RDS_HLD
RW_HLD
ADSN_SET
RW_SET
RDS_SET
RDA_DEL
CS_HLD
MPI_CLK
RDA_HLD
ADDR
DATA
D[7:0]
MPI_RW (W/R)
CS0, CS1
BE0, BE1
BE_SET
BE_HLD
MPI_ALE (ALE)
MPI_STRB (ADS)
UA[3:0]
UA_DEL
URDWR_DEL
URDWRN
RDYRCV_DELZ
RDYRCV_DEL
RDYRCV_DEL
MPI_ACK (RDYRCV)
5-5831(F).c
Figure 73.
Timing
MPI i960 Internal Read
CS_SET
A_HLD
WD_HLD
RW_HLD
CS_HLD
ADSN_HLD
A_SET
ADSN_SET
RW_SET
WD_SET
MPI_CLK
D[7:0]
ADDR
DATA
MPI_RW (W/R)
CS0, CS1
MPI_ALE (ALE)
MPI_STRB (ADS)
UA[3:0]
UA_DEL
URDWR_DEL
RDYRCV_DEL
URDWRN
RDYRCV_DEL
RDYRCV_DELZ
MPI_ACK (RDYRCV)
5-5830(F).c
Figure 74.
MPI i960 Internal Write Timing
120
Lucent Technologies Inc.
AGERE [ AGERE SYSTEMS ]
