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OR3T80-6PS240 参数 Datasheet PDF下载

OR3T80-6PS240图片预览
型号: OR3T80-6PS240
PDF下载: 下载PDF文件 查看货源
内容描述: 3C和3T现场可编程门阵列 [3C and 3T Field-Programmable Gate Arrays]
分类和应用: 现场可编程门阵列可编程逻辑
文件页数/大小: 210 页 / 4391 K
品牌: AGERE [ AGERE SYSTEMS ]
 浏览型号OR3T80-6PS240的Datasheet PDF文件第117页浏览型号OR3T80-6PS240的Datasheet PDF文件第118页浏览型号OR3T80-6PS240的Datasheet PDF文件第119页浏览型号OR3T80-6PS240的Datasheet PDF文件第120页浏览型号OR3T80-6PS240的Datasheet PDF文件第122页浏览型号OR3T80-6PS240的Datasheet PDF文件第123页浏览型号OR3T80-6PS240的Datasheet PDF文件第124页浏览型号OR3T80-6PS240的Datasheet PDF文件第125页  
Data Sheet  
June 1999  
ORCA Series 3C and 3T FPGAs  
Timing Characteristics (continued)  
Table 50. Programmable Clock Manager (PCM) Timing Characteristics (Preliminary Information)  
DD  
A < 70 °C; Industrial: VDD = 5.0 V ± 10%, –40 °C < TA < +85 °C.  
T
OR3Cxx Commercial: V  
= 5.0 V ± 5%, 0 °C  
DD = 3.0 V to 3.6 V, 0 °C < TA < 70 °C; Industrial: VDD = 3.0 V to 3.6 V, –40 °C < TA < +85 °C.  
OR3Txxx Commercial: V  
Speed  
Parameter  
Symbol  
-4  
-5  
-6  
-7  
Unit  
Min  
Max  
Min  
Max  
Min  
Max  
Min  
Max  
Input Clock Frequency:  
OR3Cxx  
FPCMI  
5
133  
5
5
133  
133  
5
5
MHz  
OR3Txxx  
133  
133 MHz  
Output Clock Frequency:  
OR3Cxx  
FPCMO  
5
135  
5
5
135  
100  
5
5
MHz  
OR3Txxx  
100  
100 MHz  
Input Clock Duty Cycle  
Output Clock Duty Cycle  
Input Frequency Tolerance*  
PCMI_DUTY  
PCMO_DUTY  
FTOL  
30.00 70.00 30.00 70.00 30.00 70.00 30.00 70.00  
3.13 96.90 3.13 96.90 3.13 96.90 3.13 96.90  
%
%
26400  
100  
26400  
100  
26400  
100  
26400 ppm  
PCM Acquisition Time (CLK In to  
LOCK)  
PCM_ACQ†  
36  
36  
36  
36  
100  
µs  
PCM Off Delay (config. Done-L, WE to  
PCM power off)  
PCMOFF_DEL  
PCMDLL-DEL  
PCMPLL_DEL  
PCMBYE_DEL  
PCMBYS_DEL  
RTCKD_DEL  
100.0  
1.95  
0.00  
0.47  
0.47  
1.30  
2.70  
100.0  
1.82  
0.00  
0.36  
0.36  
1.10  
2.20  
100.0  
1.63  
0.00  
0.26  
0.26  
0.90  
1.90  
100.0 ns  
PCM Delay in DLL Mode (propagation  
delay)  
1.50  
0.00  
0.24  
0.24  
TBD  
ns  
ns  
ns  
ns  
ns  
PCM Delay in PLL Mode (propagation  
delay)  
PCM Clock In to PCM Clock Out  
(CLK In to ECLK)‡  
PCM Clock In to PCM Clock Out  
(CLK In to SCLK)‡  
Routed Clock-in Delay (routing to PCM  
phase detect, using DIV0)  
System Clock-out Delay (PCM oscilla- PCMSCK_DEL  
tor to SCLK output at PCM)  
TBD ns  
Parameter  
Symbol  
fOUT (MHz)  
PLL Mode  
DLL Mode  
Unit  
Output Jitter  
OUTJIT  
5—20  
21—30  
31—40  
41—50  
51—60  
61—70  
71—80  
81—90  
91—100  
250  
210  
180  
155  
130  
110  
95  
200  
170  
145  
123  
105  
90  
75  
65  
55  
ps  
ps  
ps  
ps  
ps  
ps  
ps  
ps  
ps  
80  
70  
* Input frequency tolerance is the allowed input clock frequency change in parts per million.  
† See Table 29 and Table 30 for acquisition times for individual frequencies.  
‡ PLL mode, divider reg = 1111111 (input freq. = output freq.).  
Note: All timing values for the PCM are preliminary information.  
Lucent Technologies Inc.  
121  
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