Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Programmable Logic Cells (continued)
Softwired LUT submode uses F4 and F5 LUTs and internal PFU feedback routing to generate complex logic func-
tions up to three LUT-levels deep. Figure 3 shows multiplexers between the KZ[3:0] inputs to the PFU and the
LUTs. These multiplexers can be independently configured to route certain LUT outputs to the input of other LUTs.
In this manner, very complex logic functions, some of up to 21 inputs, can be implemented in a single PFU at
greatly enhanced speeds.
Figure 5 shows several softwired LUT topologies. In this figure, each circle represents either an F4 or F5 LUT. It is
important to note that an LUT output that is fed back for softwired use is still available to be registered or output
from the PFU. This means, for instance, that a logic equation that is needed by itself and as a term in a larger
equation need only be generated once and PLC routing resources will not be required to use it in the larger equa-
tion.
F4
F4
F4
F4
F4
F4
F4
F4
F5
F5
F5
F5
FOUR 7-INPUT FUNCTIONS IN ONE PFU
F5
TWO 9-INPUT FUNCTIONS IN ONE PFU
F4
F4
F4
F4
F5
F5
F5
F5
F5
ONE 17-INPUT FUNCTION IN ONE PFU
ONE 21-INPUT FUNCTION IN ONE PFU
5-5753(F)
F4
F4
F4
F4
3
F4
F4
F4
F4
TWO OF FOUR 10-INPUT FUNCTIONS IN ONE PFU
KEY:
ONE OF TWO 12-INPUT FUNCTIONS IN ONE PFU
5-5754(F)
F4 4-INPUT LUT
F5 5-INPUT LUT
Figure 5. Softwired LUT Topology Examples
Lucent Technologies Inc.
15
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