欢迎访问ic37.com |
会员登录 免费注册
发布采购

OR3T55-6BA256 参数 Datasheet PDF下载

OR3T55-6BA256图片预览
型号: OR3T55-6BA256
PDF下载: 下载PDF文件 查看货源
内容描述: 3C和3T现场可编程门阵列 [3C and 3T Field-Programmable Gate Arrays]
分类和应用: 现场可编程门阵列可编程逻辑
文件页数/大小: 210 页 / 4391 K
品牌: AGERE [ AGERE SYSTEMS ]
 浏览型号OR3T55-6BA256的Datasheet PDF文件第12页浏览型号OR3T55-6BA256的Datasheet PDF文件第13页浏览型号OR3T55-6BA256的Datasheet PDF文件第14页浏览型号OR3T55-6BA256的Datasheet PDF文件第15页浏览型号OR3T55-6BA256的Datasheet PDF文件第17页浏览型号OR3T55-6BA256的Datasheet PDF文件第18页浏览型号OR3T55-6BA256的Datasheet PDF文件第19页浏览型号OR3T55-6BA256的Datasheet PDF文件第20页  
Data Sheet  
June 1999  
ORCA Series 3C and 3T FPGAs  
with half-logic ripple connections shown as dashed  
lines.  
Programmable Logic Cells (continued)  
Half-Logic Mode  
The result output and ripple output are calculated by  
using generate/propagate circuitry. In ripple mode, the  
two operands are input into KZ[1] and KZ[0] of each  
LUT. The result bits, one per LUT, are F[7:0]/F[3:0] (see  
Figure 6). The ripple output from LUT K7/K3 can be  
routed on dedicated carry circuitry into any of four adja-  
cent PLCs, and it can be placed on the PFU COUT/  
FCOUT outputs. This allows the PLCs to be cascaded  
in the ripple mode so that nibble-wide ripple functions  
can be expanded easily to any length.  
Series 3 FPGAs are based upon a twin-quad architec-  
ture in the PFUs. The byte-wide nature (eight LUTs,  
eight latches/FFs) may just as easily be viewed as two  
nibbles (two sets of four LUTs, four latches/FFs). The  
two nibbles of the PFU are organized so that any nib-  
ble-wide feature (excluding some softwired LUT topolo-  
gies) can be swapped with any other nibble-wide  
feature in another PFU. This provides for very flexible  
use of logic and for extremely flexible routing. The half-  
logic mode of the PFU takes advantage of the twin-  
quad architecture and allows half of a PFU, K[7:4] and  
associated latches/FFs, to be used in logic mode while  
the other half of the PFU, K[3:0] and associated latches/  
FFs, is used in ripple mode. In half-logic mode, the  
ninth FF may be used as a general-purpose FF or as a  
register in the ripple mode carry chain.  
Result outputs and the carry-out may optionally be reg-  
istered within the PFU. The capability to register the  
ripple results, including the carry output, provides for  
improved counter performance and simplified pipelin-  
ing in arithmetic functions.  
Ripple Mode  
REGCOUT  
D
Q
C
C
The PFU LUTs can be combined to do byte-wide ripple  
functions with high-speed carry logic. Each LUT has a  
dedicated carry-out net to route the carry to/from any  
adjacent LUT. Using the internal carry circuits, fast  
arithmetic, counter, and comparison functions can be  
implemented in one PFU. Similarly, each PFU has  
carry-in (CIN, FCIN) and carry-out (COUT, FCOUT)  
ports for fast-carry routing between adjacent PFUs.  
FCOUT  
COUT  
F7  
K7[1]  
K7[0]  
D
D
D
D
D
D
D
D
K7  
K6  
K5  
K4  
K3  
K2  
K1  
K0  
Q7  
Q
Q
Q
Q
Q
Q
Q
Q
F6  
K6[1]  
K6[0]  
Q6  
The ripple mode is generally used in operations on two  
data buses. A single PFU can support an 8-bit ripple  
function. Data buses of 4 bits and less can use the  
nibble-wide ripple chain that is available in half-logic  
mode. This nibble-wide ripple chain is also useful for  
longer ripple chains where the length modulo 8 is four  
or less. For example, a 12-bit adder (12 modulo 8 = 4)  
can be implemented in one PFU in ripple mode (8 bits)  
and one PFU in half-logic mode (4 bits), freeing half of  
a PFU for general logic mode functions.  
F5  
K5[1]  
K5[0]  
Q5  
F4  
K4[1]  
K4[0]  
Q4  
F3  
K3[1]  
K3[0]  
Q3  
F2  
K2[1]  
K2[0]  
Q2  
Each LUT has two operands and a ripple (generally  
carry) input, and provides a result and ripple (generally  
carry) output. A single bit is rippled from the previous  
LUT and is used as input into the current LUT. For LUT  
K0, the ripple input is from the PFU CIN or FCIN port.  
The CIN/FCIN data can come from either the fast-carry  
routing (FCIN) or the PFU input (CIN), or it can be tied  
to logic 1 or logic 0.  
F1  
K1[1]  
K1[0]  
Q1  
F0  
K0[1]  
K0[0]  
Q0  
CIN/FCIN  
5-5755(F)  
In the following discussions, the notations LUT K7/K3  
and F[7:0]/F[3:0] are used to denote the LUT that pro-  
vides the carry-out and the data outputs for full PFU  
ripple operation (K7, F[7:0]) and half-logic ripple  
operation (K3, F[3:0]), respectively. The ripple mode  
diagram in Figure 6 shows full PFU ripple operation,  
Figure 6. Ripple Mode  
16  
Lucent Technologies Inc.