Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Programmable Logic Cells
F5D
The programmable logic cell (PLC) consists of a pro-
grammable function unit (PFU), a supplemental logic
and interconnect cell (SLIC), and routing resources. All
PLCs in the array are functionally identical with only
minor differences in routing connectivity for improved
routability. The PFU, which contains eight 4-input LUTs,
eight latches/FFs, and one FF for logic implementation,
is discussed in the next section, followed by discus-
sions of the SLIC and PLC routing resources.
K7_0
K7_1
K7_2
K7_3
K6_0
K6_1
K6_2
K6_3
K5_0
K5_1
K5_2
K5_3
K4_0
K4_1
K4_2
K4_3
Programmable Function Unit
Q7
Q6
Q5
Q4
Q3
Q2
Q1
The PFUs are used for logic. Each PFU has 50 external
inputs and 18 outputs and can operate in several
modes. The functionality of the inputs and outputs
depends on the operating mode.
F5C
DIN7
DIN6
DIN5
DIN4
DIN3
DIN2
DIN1
DIN0
Q0
The PFU uses 36 data input lines for the LUTs, eight
data input lines for the latches/FFs, five control inputs
(ASWE, CLK, CE, LSR, SEL), and a carry input (CIN)
for fast arithmetic functions and general-purpose data
input for the ninth FF. There are eight combinatorial data
outputs (one from each LUT), eight latched/registered
outputs (one from each latch/FF), a carry-out (COUT),
and a registered carry-out (REGCOUT) that comes from
the ninth FF. The carry-out signals are used principally
for fast arithmetic functions.
PROGRAMMABLE
FUNCTION UNIT
(PFU)
COUT
REGCOUT
CIN
F5B
F7
F6
F5
F4
F3
F2
F1
F0
K3_0
K3_1
K3_2
K3_3
K2_0
K2_1
K2_2
K2_3
Figure 2 and Figure 3 show high-level and detailed
views of the ports in the PFU, respectively. The eight
sets of LUT inputs are labeled as K0 through K7 with
each of the four inputs to each LUT having a suffix of
_x, where x is a number from 0 to 3. There are four F5
inputs labeled A through D. These inputs are used for a
fifth LUT input for 5-input LUTs or as a selector for multi-
plexing two 4-input LUTs. The eight direct data inputs to
the latches/FFs are labeled as DIN[7:0]. Registered LUT
outputs are shown as Q[7:0], and combinatorial LUT
outputs are labeled as F[7:0].
K1_0
K1_1
K1_2
K1_3
K0_0
K0_1
K0_2
K0_3
F5A
LSR CLK
CE
SEL ASWE
The PFU implements combinatorial logic in the LUTs
and sequential logic in the latches/FFs. The LUTs are
static random access memory (SRAM) and can be used
for read/write or read-only memory.
5-5752(F)
5-5752(F)
Figure 2. PFU Ports
Each latch/FF can accept data from its associated LUT.
Alternatively, the latches/FFs can accept direct data
from DIN[7:0], eliminating the LUT delay if no combina-
torial function is needed. Additionally, the CIN input can
be used as a direct data source for the ninth FF. The
LUT outputs can bypass the latches/FFs, which reduces
the delay out of the PFU. It is possible to use the LUTs
and latches/FFs more or less independently, allowing,
for instance, a comparator function in the LUTs simulta-
neously with a shift register in the FFs.
The PFU can be configured to operate in four modes:
logic mode, half-logic mode, ripple mode, and memory
(RAM/ROM) mode. In addition, ripple mode has four
submodes and RAM mode can be used in either a
single- or dual-port memory fashion. These submodes
of operation are discussed in the following sections.
Lucent Technologies Inc.
11
AGERE [ AGERE SYSTEMS ]
