Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Timing Characteristics (continued)
Table 58. OR3C/Txxx Input to Fast Clock Setup/Hold Time (Pin-to-Pin) (continued)
DD
5
<
A
<
DD
<
A
<
OR3Cxx Commercial: V = .0 V ± 5%, 0 °C
T
70 °C; Industrial: V = 5.0 V ± 10%, –40 °C
T
+85 °C.
DD
<
A
<
DD
<
A
<
OR3Txxx Commercial: V = 3.0 V to 3.6 V, 0 °C
T
70 °C; Industrial: V = 3.0 V to 3.6 V, –40 °C
T
+85 °C.
Speed
Description
Device
Unit
-4
-5
-6
-7
J
DD
(T = 85 °C, V = min)
Min
Max
Min
Max
Min
Max
Min
Max
Input to FCLK Hold Time (middle
ECLK pin, delayed data input)
ns
ns
ns
ns
ns
OR3T20
OR3T30
OR3C/T55
OR3C/T80
OR3T125
—
—
0.00
0.00
—
—
—
—
—
—
0.00
0.00
0.00
0.00
0.00
—
—
—
—
—
0.00
0.00
0.00
0.00
0.00
—
—
—
—
—
0.00
0.00
0.00
0.00
0.00
—
—
—
—
—
Input to FCLK Hold Time (corner
ECLK pin)
ns
ns
ns
ns
ns
OR3T20
OR3T30
OR3C/T55
OR3C/T80
OR3T125
—
—
8.43
9.09
—
—
—
—
—
—
6.26
6.49
6.98
7.53
8.45
—
—
—
—
—
5.54
5.72
6.09
6.47
7.10
—
—
—
—
—
4.88
5.04
5.40
5.79
6.40
—
—
—
—
—
Input to FCLK Hold Time (corner
ECLK pin, delayed data input)
ns
ns
ns
ns
ns
OR3T20
OR3T30
OR3C/T55
OR3C/T80
OR3T125
—
—
0.00
0.00
—
—
—
—
—
—
0.00
0.00
0.00
0.00
0.00
—
—
—
—
—
0.00
0.00
0.00
0.00
0.00
—
—
—
—
—
0.00
0.00
0.00
0.00
0.00
—
—
—
—
—
Notes:
ORCA
The pin-to-pin timing parameters in this table should be used instead of results reported by
Foundry.
The FCLK delays are for a fully routed clock tree that uses the ExpressCLK input into the fast clock network. It includes both the input buffer
delay and the clock routing to the PFU CLK input. The delay will be reduced if any of the clock branches are not used.
PIO FF
INPUT
ECLK
D
Q
CLKCNTRL
FCLK
5-4847(F).a
Figure 80. Input to Fast Clock Setup/Hold Time
Lucent Technologies Inc.
131
AGERE [ AGERE SYSTEMS ]
