Advance Data Sheet
March 2001
CA16-Type 2.5 Gbits/s DWDM Transponder with
16-Channel 155 Mbits/s Multiplexer/Demultiplexer
Timing Characteristics (continued)
reference clock to the internal load signal over temper-
ature and voltage. The connections required to imple-
ment this clocking method are shown in Figure 7. The
setup and hold times for PICLK to TxD[0:15] must be
met by the customer logic.
Forward Clocking
In some applications, it is necessary to forward-clock
the data in a SONET/SDH system. In this application,
the reference clock from which the high-speed serial
clock is synthesized and the parallel data clock both
originate from the same source on the customer appli-
cation circuit. The timing control logic in the CA16 tran-
sponder transmitter automatically generates an internal
load signal that has a fixed relationship to the reference
clock. The logic takes into account the variation of the
Possible problems: to meet the jitter generation specifi-
cations required by SONET/SDH, the jitter of the refer-
ence clock must be minimized. It could be difficult to
meet the SONET jitter generation specifications using
a reference clock generated from the customer logic.
OSCILLATOR
155.52 MHz ± 20 ppm
CLOCK
BUFFER
TXREFCLK
TXREFCLK
PCLK
DIVIDER
PLL
INTERNAL
PCLK
PICLK
CLOCK
TXD[0:15]
16
DATA
FIFO
TIMING
GENERATOR
CENTERS
FIFO
PHERR
PHINIT
LOCKDET
CUSTOMER LOGIC
CA16 TRANSPONDER
1-1122(F).a
Figure 7. Forward Clocking of the CA16Transponder
21
Agere Systems Inc.
AGERE [ AGERE SYSTEMS ]
