CA16-Type 2.5 Gbits/sDWDMTransponder with
16-Channel 155 Mbits/s Multiplexer/Demultiplexer
Advance Data Sheet
March 2001
dummy bytes to the CA16 on the TXD[0:15] bus. This
should continue until PHERR goes low.
Transmitter Data Input Timing (continued)
Input Timing Mode 2
The FIFO is initialized two-to-eight byte clocks after
PHINIT goes high for two byte clocks. PHERR goes low
after the FIFO is initialized. Upon detecting a low on
PHERR, the customer logic can start sending real data
bytes on TXD[0:15]. The two timing loops (PCLK to
PICLK and PHERR to PHINIT) do not have to be of
equal length.
To avoid the loss of data, idle or dummy bytes should
be sent on the TXD[0:15] bus whenever PHERR goes
high. In the configuration shown in Figure 6, the
PHERR signal is used as an input to the customer
logic. Upon detecting a high on the PHERR signal, the
customer logic should return a high signal, one that
remains high for at least two byte-clock cycles, to the
PHINIT input of the CA16. Also, when PHERR goes
high, the customer logic should start sending idle or
OSCILLATOR
155.52 MHz ± 20 ppm
TXREFCLK
PCLK
DIVIDER
PLL
INTERNAL
PCLK
PICLK
CLOCK
TXD[0:15]
16
DATA
FIFO
TIMING
GENERATOR
PHERR
PHINIT
CENTERS
FIFO
D
Q
LOCKDET
CUSTOMER LOGIC
CA16 TRANSPONDER
1121(F).b
Figure 6. Block Diagram Timing Mode 2
20
20
Agere Systems Inc.
AGERE [ AGERE SYSTEMS ]
