Advance Data Sheet
March 2001
CA16-Type 2.5 Gbits/s DWDM Transponder with
16-Channel 155 Mbits/s Multiplexer/Demultiplexer
Timing Characteristics (continued)
Since the delay in the customer ASIC is unknown, the
two clocks (PCLK and PICLK) might drift in respect to
each other and try to perform the read and writer oper-
ation on the same bank in the FIFO at the same time.
However, before such a clock mismatch can occur,
Input Timing Mode 1
In the configuration shown in Figure 5, PHERR to
PHINIT has a zero delay (shorted on the PCB) and the
PCLK is used to clock 16-bit-wide data out of the cus-
tomer ASIC. The FIFO in the multiplexer ia 16-bits wide
and six registers deep.
PHERR goes high and, if externally connected to
PHINIT, will initialize the FIFO provided PHINIT
remains high for at least two byte clocks. One to three
16-bit words of data will be lost during the initialization
of the FIFO.
The PCLK and PICLK signals respectively control the
READ and WRITE counters for the FIFO. The data
bank from the FIFO has to be read by the internally
generated clock (PCLK) only once after it has been writ-
ten by the PICLK input.
OSCILLATOR
155.52 MHz ± 20 ppm
TXREFCLK
PCLK
DIVIDER
PLL
INTERNAL
PCLK
PICLK
CLOCK
TXD[0:15]
16
DATA
FIFO
TIMING
GENERATOR
PHERR
PHINIT
CENTERS
FIFO
D
Q
LOCKDET
CUSTOMER LOGIC
CA16 TRANSPONDER
1-1121(F).b
Figure 5. Block Diagram Timing Mode 1
19
Agere Systems Inc.
AGERE [ AGERE SYSTEMS ]
