Advance Data Sheet
March 2001
CA16-Type 2.5 Gbits/s DWDM Transponder with
16-Channel 155 Mbits/s Multiplexer/Demultiplexer
Case 2—PHERR signal is input to the customer logic
and the customer logic outputs a signal to PHINIT:
Timing Characteristics (continued)
PHERR/PHINIT
Another possible configuration is where the PHERR
signal is input into the customer logic and the customer
logic sends an output to the PHINIT input. However,
the customer logic must ensure that, upon detecting a
high on PHERR, the PHINIT signal remains high for
more than two byte clocks. If PHINIT is high for less
than two byte clocks, the FIFO is not guaranteed to be
initialized. Also, the customer logic must ensure that
PHINIT goes low after the FIFO is initialized (PHERR
goes low).
Case 1—PHERR and PHINIT are shorted on the
printed-circuit board:
PHINIT would go high whenever there is a potential tim-
ing mismatch between PCLK and PICLK. PHINIT would
remain high as long as the timing mismatch between
PCLK and PICLK. If PHINIT is high for more than two
byte clocks, the FIFO will be initialized. PHINIT will ini-
tialize the FIFO two-to-eight byte clocks after it is high
for at least two byte clocks, PHERR (and thus PHINIT)
goes active once the FIFI is initialized.
2 BYTE
CLOCKS
2—8 BYTE CLOCKS
PHERR
MINIMUM PULSE
WIDTH REQUIRED
TO CENTER
THE FIFO
CUSTOMER ASIC SENDS A
MINIMUM PULSE WIDTH OF
2 BYTE CLOCKS UPON DETECTING
A HIGH ON PHERR
PHINIT
PCLK
PICLK
INTERNAL
PCLK
PHERR GOES HIGH ON
FIFO IS INITIALIZED 2—8 BYTE CLOCKS
DETECTING A FIFO TIMING ERROR
AFTER PHINIT IS HIGH FOR 2 BYTE CLOCKS
1125(F)
Figure 9. PHERR/PHINIT Timing
23
Agere Systems Inc.
AGERE [ AGERE SYSTEMS ]
