Data Sheet
AD5940
INTERRUPTS
There are a number of interrupt options available on the AD5940.
These interrupts can be configured to toggle a GPIOx pin in
response to an interrupt event.
CUSTOM INTERRUPTS
Four custom interrupt sources are selectable by the user in
INTCSELx, Bits[12:9]). These custom interrupts can generate
an interrupt event by writing to the corresponding bit in the
AFEGENINTSTA register. It is only possible to write to this
register via the sequencer. Writing to the AFEGENINTSTA
register when using the SPI has no effect.
INTERRUPT CONTROLLER INTERUPTS
The interrupt controller is divided into two blocks. Each block
consists of an INTCSELx register and an INTCFLAGx register.
The INTCPOL and INTCCLR registers are common to both
blocks. After an interrupt is enabled in the INTCSELx register,
the corresponding bit in the INTCFLAGx register is set. The
available interrupt sources are shown in Table 134. The
INTCFLAGx interrupts can be configured to toggle a
GPIOx pin in response to an interrupt event.
EXTERNAL INTERRUPT CONFIGURATION
Eight external interrupts are implemented on the AD5940.
These external interrupts can be configured to detect any
combination of the following types of events:
•
•
•
•
•
Rising edge. The logic detects a transition from low to high
and generates a pulse.
Falling edge. The logic detects a transition from high to
low and generates a pulse.
Rising or falling edge. The logic detects a transition from
low to high or high to low and generates a pulse.
High level. The logic detects a high level. The interrupt line
is held asserted until the external source deasserts.
Low level. The logic detects a low level. The interrupt line
is held asserted until the external source deasserts.
CONFIGURING THE INTERRUPTS
Before configuring the interrupt sources, the GPIOx pin must
be configured as the interrupt output. GPIO0, GPIO3, and
GPIO6 can be configured for the INT0 output. GPIO4 and
GPIO7 can be configured for the INT1 output. Refer to the
Digital Port Multiplex section for more details. The user can
program the polarity of the interrupt (rising or falling edge) in
the INTCPOL register. When an interrupt is triggered, the
selected GPIOx pin toggles to alert the host microcontroller
that an interrupt event has occurred. To clear an interrupt
source, write to the corresponding bit in the INTCCLR register.
The external interrupt detection unit block allows an external
event to wake up the AD5940 when it is in hibernate mode.
Table 134. Interrupt Sources Summary
INTCFLAGx Register Flag Name Interrupt Source Description
FLAG0
ADC result IRQ status.
FLAG1
DFT result IRQ status.
FLAG2
FLAG3
FLAG4
FLAG5
FLAG6
FLAG7
Sinc2 filter result ready IRQ status.
Temperature result IRQ status.
ADC minimum fail IRQ status.
ADC maximum fail IRQ status.
ADC delta fail IRQ status.
Mean IRQ status.
FLAG8
Variance IRQ status.
FLAG13
FLAG15
FLAG16
FLAG17
FLAG23
FLAG24
FLAG25
FLAG26
FLAG27
FLAG29
FLAG31
Bootload done IRQ status.
End of sequence IRQ status.
Sequencer timeout finished IRQ status. See the Timer Command section.
Sequencer timeout command error IRQ status. See the Timer Command section.
Data FIFO full IRQ status.
Data FIFO empty IRQ status.
Data FIFO threshold IRQ status. Threshold value set in DATAFIFOTHRES register.
Data FIFO overflow IRQ status.
Data FIFO underflow IRQ status.
Outlier IRQ status. Detects when an outlier is detected.
Attempt to break IRQ status. This interrupt is set if a Sequence B request occurs when Sequence A is
running. This interrupt indicates that Sequence B is ignored.
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