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EVAL-AD5570EB 参数 Datasheet PDF下载

EVAL-AD5570EB图片预览
型号: EVAL-AD5570EB
PDF下载: 下载PDF文件 查看货源
内容描述: 真正的精度, 16位12 V / 15 V ,串行输入电压输出DAC [True Accuracy, 16-Bit 12 V/15 V, Serial Input Voltage Output DAC]
分类和应用:
文件页数/大小: 24 页 / 1039 K
品牌: ADI [ ADI ]
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AD±±70  
STANDALONE TIMING CHARACTERISTICS  
VDD = +1ꢀ V 5ꢂ, VSS = −1ꢀ V 5ꢂ or VDD = +15 V 10ꢂ, VSS = −15 V 10ꢂ; VREF = 5 V; REFGND = GND = 0 V; RL = 5 kΩ;  
and CL = ꢀ00 pF to GND; all specifications TMIN to TMAX, unless otherwise noted.  
Table 2.  
Parameter  
Limit at TMIN, TMAX  
Unit  
Description  
fMAX  
t1  
t2  
t3  
t4  
10  
100  
35  
35  
10  
35  
0
45  
45  
0
MHz max  
ns min  
ns min  
ns min  
ns min  
ns min  
ns min  
ns min  
ns min  
ns min  
ns min  
ns min  
ns min  
ns min  
SCLK frequency  
SCLK cycle time  
SCLK high time  
SCLK low time  
SYNC to SCLK falling edge setup time  
Data setup time  
Data hold time  
SCLK falling edge to SYNC rising edge  
Minimum SYNC high time  
SYNC rising edge to LDAC falling edge  
LDAC pulse width  
t5  
t6  
t±  
tꢁ  
tꢀ  
t10  
t11  
t12  
t13  
50  
0
LDAC falling edge to SYNC falling edge (no update)  
LDAC rising edge to SYNC rising edge (no update)  
CLR pulse width  
0
20  
All parameters guaranteed by design and characterization. Not production tested.  
All input signals are measured with tr = tf = 5 ns (10% to ꢀ0% of VDD) and timed from a voltage level of (VIL +VIH)/2.  
t1  
SCLK  
t2  
t3  
t8  
t4  
t7  
SYNC  
SDIN  
t6  
t5  
DB15  
DB0  
t9  
t10  
1
LDAC  
t11  
t12  
2
LDAC  
t13  
CLR  
NOTES  
1. ASYNCHRONOUS LDAC UPDATE MODE. UPDATE ON FALLING EDGE OF LDAC.  
2. SYNCHRONOUS LDAC UPDATE MODE. UPDATE ON RISING EDGE OF SYNC.  
Figure 2. Serial Interface Timing Diagram  
Rev. 0 | Page 5 of 24  
 
 
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