AD±±70
DAISY-CHAINING AND READBACK TIMING CHARACTERISTICS
VDD = +1ꢀ V 5ꢂ, VSS = −1ꢀ V 5ꢂ or VDD = +15 V 10ꢂ, VSS = −15 V 10ꢂ; VREF = 5 V; REFGND = GND = 0 V; RL = 5 kΩ,
and CL = ꢀ00 pF to GND; all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter
Limit at TMIN, TMAX
Unit
Description
fMAX
t1
t2
t3
t4
2
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
SCLK frequency
SCLK cycle time
SCLK high time
SCLK low time
SYNC to SCLK falling edge setup time
Data setup time
Data hold time
SCLK falling edge to SYNC rising edge
Minimum SYNC high time
SYNC rising edge to LDAC falling edge
LDAC pulse width
500
200
200
10
35
0
45
45
0
t5
t6
t±
tꢁ
tꢀ
t10
50
1
t14
200
Data delay on SDO
All parameters guaranteed by design and characterization. Not production tested.
All input signals are measured with tr = tf = 5 ns (10% to ꢀ0% of VDD) and timed from a voltage level of (VIL +VIH)/2.
SDOꢂ RPULLUP = 5 kΩ, CL = 15 pF.
1 With CL = 0 pF, t15 = 100 ns.
t1
SCLK
t3
t2
t4
t7
t8
SYNC
t10
1
LDAC
t9
2
LDAC
t6
t5
DB0
(N+1)
DB15
(N+1)
DB15 (N)
DB0 (N)
SDIN
SDO
t14
DB15
(N+1)
DB15 (N)
DB0 (N)
NOTES
1. ASYNCHRONOUS LDAC UPDATE MODE
2. SYNCHRONOUS LDAC UPDATE MODE
Figure 3. Daisy-Chaining Timing Diagram
Rev. 0 | Page 6 of 24
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