ADV7390/ADV7391/ADV7392/ADV7393
DISPLAY
DISPLAY
VERTICAL BLANK
3
4
5
7
622
623
624
625
1
2
6
21
22
23
HSYNC
FIELD
ODD FIELD
EVEN FIELD
DISPLAY
DISPLAY
VERTICAL BLANK
309
310
311
312
313
314
315
316
318
319
320
317
334
335
336
HSYNC
FIELD
ODD FIELD
EVEN FIELD
Figure 107. SD Timing Mode 1, Slave Option, PAL
Mode 1—Master Option (Subaddress 0x8A = X X X X X 0 1 1)
In this mode, the ADV739x can generate horizontal synchronization and odd/even field signals. When
HSYNC
is low, a transition of the
field input indicates a new frame, that is, vertical retrace. The ADV739x automatically blanks all normally blank lines as per CCIR-624.
HSYNC HSYNC
Pixel data is latched on the rising clock edge following the timing signal transitions.
and FIELD are output on the
and
VSYNC
pins, respectively.
HSYNC
FIELD
PIXEL
DATA
Cr
Y
Cb
Y
PAL = 132 × CLOCK/2
NTSC = 122 × CLOCK/2
Figure 108. SD Timing Mode 1, Odd/Even Field Transitions (Master/Slave)
Mode 2— Slave Option (Subaddress 0x8A = X X X X X 1 0 0)
In this mode, the ADV739x accepts horizontal and vertical synchronization signals. A coincident low transition of both
VSYNC VSYNC HSYNC
HSYNC
and
is high indicates the start of an even field. The
VSYNC HSYNC VSYNC
inputs indicates the start of an odd field. A
low transition when
HSYNC
ADV739x automatically blanks all normally blank lines as per CCIR-624.
pins, respectively.
and
are input on the
and
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