ADV7390/ADV7391/ADV7392/ADV7393
APPENDIX 5–SD TIMING
Mode 0 (CCIR-656)—Slave Option (Subaddress 0x8A = X X X X X 0 0 0)
The ADV739x is controlled by the SAV (start of active video) and EAV (end of active video) time codes embedded in the pixel data. All
timing information is transmitted using a 4-byte synchronization pattern. A synchronization pattern is sent immediately before and after
VSYNC
HSYNC
each line during active picture and retrace. If the
and
pins are not used, they should be tied high when using this mode.
ANALOG
VIDEO
EAV CODE
SAV CODE
C
b
C
r
8
0
0
0
F
F
F
F
A
B
A
B
A
B
8
0
0
0
C
b
C
r
F
F
0
0
0
0
X
Y
1
0
8
0
1
0
8
0
1
0
1
0
F
F
0
0
X
Y
C
b
C
r
Y
Y
Y
Y
Y
Y
INPUT PIXELS
ANCILLARY DATA
(HANC)
4 CLOCK
4 CLOCK
4 CLOCK
4 CLOCK
1440 CLOCK
1440 CLOCK
268 CLOCK
NTSC/PAL M SYSTEM
(525 LINES/60Hz)
280 CLOCK
PAL SYSTEM
(625 LINES/50Hz)
START OF ACTIVE
VIDEO LINE
END OF ACTIVE
VIDEO LINE
Figure 102. SD Timing Mode 0, Slave Option
Mode 0 (CCIR-656)—Master Option (Subaddress 0x8A = X X X X X 0 0 1)
The ADV739x generates H and F signals required for the SAV and EAV time codes in the CCIR-656 standard. The H bit is output on
HSYNC
VSYNC
and the F bit is output on
.
DISPLAY
DISPLAY
VERTICAL BLANK
4
522
523
524
525
1
2
3
5
6
7
8
10
11
20
21
22
9
H
F
ODD FIELD
EVEN FIELD
DISPLAY
DISPLAY
VERTICAL BLANK
283
285
284
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
H
F
ODD FIELD
EVEN FIELD
Figure 103. SD Timing Mode 0, Master Option, NTSC
Rev. 0 | Page 72 of 96
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