ADV7390/ADV7391/ADV7392/ADV7393
APPENDIX 3–SD CLOSED CAPTIONING
All pixels inputs are ignored on Line 21 and Line 284 if closed
captioning is enabled.
Subaddress 0x91 to Subaddress 0x94
The ADV739x supports closed captioning conforming to the
standard television synchronizing waveform for color
transmission. When enabled, closed captioning is transmitted
during the blanked active line time of Line 21 of the odd fields
and Line 284 of the even fields. Closed captioning can be
enabled using Subaddress 0x83, Bits[6:5].
The FCC Code of Federal Regulations (CFR) Title 47 Section
15.119 and EIA-608 describe the closed captioning information
for Line 21 and Line 284.
The ADV739x uses a single buffering method. This means that
the closed captioning buffer is only 1-byte deep. Therefore,
there is no frame delay in outputting the closed captioning data
unlike other 2-byte deep buffering systems. The data must be
loaded one line before it is output on Line 21 and Line 284. A
Closed captioning consists of a 7-cycle sinusoidal burst that is
frequency and phase-locked to the caption data. After the clock
run-in signal, the blanking level is held for two data bits and is
followed by a Logic 1 start bit. Sixteen bits of data follow the start
bit. The data consists of two 8-bit bytes (seven data bits, and one
odd parity bit per byte). The data for these bytes is stored in SD
closed captioning registers (Subaddress 0x93 to Subaddress 0x94).
VSYNC
typical implementation of this method is to use
to
interrupt a microprocessor, which in turn loads the new data
(2 bytes) in every field. If no new data is required for transmis-
sion, 0s must be inserted in both data registers; this is called
nulling. It is also important to load control codes, all of which
are double bytes, on Line 21. Otherwise, a TV does not recognize
them. If there is a message such as “Hello World” that has an
odd number of characters, it is important to add a blank
character at the end to make sure that the end-of-caption,
2-byte control code lands in the same field.
The ADV739x also supports the extended closed captioning
operation, which is active during even fields and encoded on
Line 284. The data for this operation is stored in SD closed
captioning registers (Subaddress 0x91 to Subaddress 0x92).
The ADV739x automatically generates all clock run-in signals
and timing that support closed captioning on Line 21 and Line 284.
10.5 ± 0.25µs
12.91µs
7 CYCLES OF
0.5035MHz
CLOCK RUN-IN
TWO 7-BIT + PARITY
ASCII CHARACTERS
(DATA)
P
A
R
I
T
Y
P
A
R
I
T
Y
S
T
A
R
T
D0 TO D6
D0 TO D6
BYTE 1
50 IRE
40 IRE
BYTE 0
REFERENCE COLOR BURST
(9 CYCLES)
FREQUENCY = F = 3.579545MHz
SC
AMPLITUDE = 40 IRE
10.003µs
27.382µs
33.764µs
Figure 101. SD Closed Captioning Waveform, NTSC
Rev. 0 | Page 70 of 96
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