ADV7390/ADV7391/ADV7392/ADV7393
HSYNC
VSYNC
PAL = 864 × CLOCK/2
NTSC = 858 × CLOCK/2
PIXEL
DATA
Cb
Cr
Y
Cb
Y
PAL = 132 × CLOCK/2
NTSC = 122 × CLOCK/2
Figure 112. SD Timing Mode 2, Odd-to-Even Field Transition (Master/Slave)
Mode 3—Master/Slave Option (Subaddress 0x8A = X X X X X 1 1 0 or X X X X X 1 1 1)
HSYNC
In this mode, the ADV739x accepts or generates horizontal synchronization and odd/even field signals. When
is high, a
transition of the field input indicates a new frame, that is, vertical retrace. The ADV739x automatically blanks all normally blank lines as
HSYNC
VSYNC
HSYNC
VSYNC
and pins, respectively.
per CCIR-624.
and
are output in master mode and input in slave mode on the
DISPLAY
DISPLAY
VERTICAL BLANK
522
523
524
525
4
20
21
22
10
11
1
2
3
5
6
7
8
9
HSYNC
FIELD
EVEN FIELD ODD FIELD
DISPLAY
DISPLAY
VERTICAL BLANK
283
285
284
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
HSYNC
FIELD
ODD FIELD EVEN FIELD
Figure 113. SD Timing Mode 3, NTSC
DISPLAY
DISPLAY
VERTICAL BLANK
622
623
624
625
1
2
3
4
5
6
7
21
22
23
HSYNC
FIELD
EVEN FIELD ODD FIELD
DISPLAY
DISPLAY
VERTICAL BLANK
309
310
311
312
313
314
315
316
318
319
320
317
334
335
336
HSYNC
FIELD
EVEN FIELD ODD FIELD
Figure 114. SD Timing Mode 3, PAL
Rev. 0 | Page 76 of 96
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