ADV7390/ADV7391/ADV7392/ADV7393
DISPLAY
DISPLAY
VERTICAL BLANK
522
523
524
525
1
3
4
5
7
8
20
21
22
2
6
10
11
9
HSYNC
VSYNC
ODD FIELD
EVEN FIELD
DISPLAY
DISPLAY
VERTICAL BLANK
283
285
284
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
HSYNC
VSYNC
EVEN FIELD
ODD FIELD
Figure 109. SD Timing Mode 2, Slave Option, NTSC
DISPLAY
DISPLAY
VERTICAL BLANK
4
622
623
624
625
1
2
3
5
6
7
21
22
23
HSYNC
VSYNC
EVEN FIELD
ODD FIELD
DISPLAY
DISPLAY
VERTICAL BLANK
309
310
311
312
313
314
315
316
318
319
320
317
334
335
336
HSYNC
VSYNC
EVEN FIELD
ODD FIELD
Figure 110. SD Timing Mode 2, Slave Option, PAL
Mode 2—Master Option (Subaddress 0x8A = X X X X X 1 0 1)
In this mode, the ADV739x can generate horizontal and vertical synchronization signals. A coincident low transition of both
VSYNC
HSYNC
and
inputs indicates the start of an odd field.
VSYNC HSYNC
A
low transition when
is high indicates the start of an even field. The ADV739x automatically blanks all normally blank
VSYNC HSYNC VSYNC
HSYNC
lines as per CCIR-624.
and
are output on the
and
pins, respectively.
HSYNC
VSYNC
PIXEL
DATA
Cb
Cr
Y
Y
PAL = 132 × CLOCK/2
NTSC = 122 × CLOCK/2
Figure 111. SD Timing Mode 2, Even-to-Odd Field Transition (Master/Slave)
Rev. 0 | Page 75 of 96
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