ADV7390/ADV7391/ADV7392/ADV7393
ADV739x
CLKIN
DAC 1
DAC 2
DAC 3
LCC1
SFL
SFL/MISO
COMPOSITE
P19 TO
P10
ADV7403
VIDEO
DECODER
1
VIDEO
5
PIXEL PORT
4 BITS
RESERVED
21
0
14 BITS
SEQUENCE
4
H/L TRANSITION
COUNT START
RESET BIT
SUBCARRIER
PHASE
3
BIT
LOW
RESERVED
2
PLL INCREMENT
F
128
SC
13
0
RTC
6768
14
19
TIME SLOT 01
VALID
SAMPLE
INVALID
SAMPLE
8/LINE
LOCKED
CLOCK
5 BITS
RESERVED
1
2
FOR EXAMPLE, VCR OR CABLE.
F
PLL INCREMENT IS 22 BITS LONG. VALUE LOADED INTO ADV73xx F DDS REGISTER IS
SC
SC
F
PLL INCREMENTS BITS 21:0 PLUS BITS 0:9 OF SUBCARRIER FREQUENCY REGISTERS.
SC
3
SEQUENCE BIT
PAL: 0 = LINE NORMAL, 1 = LINE INVERTED
NTSC: 0 = NO CHANGE
RESET ADV739x DDS.
4
5
REFER TO THE ADV7390/ADV7391 AND ADV7392/ADV7393 “INPUT CONFIGURATION” TABLES FOR PIXEL DATA PIN ASSIGNMENTS.
Figure 64. SD Subcarrier Frequency Lock Timing and Connections Diagram (Subaddress 0x84, Bits [2:1] = 11)
VBI data can be present on Line 10 to Line 20 for NTSC and on
Line 7 to Line 22 for PAL.
SD VCR FF/RW SYNC
Subaddress 0x82, Bit 5
In SD Timing Mode 0 (slave option), if VBI is enabled, the
blanking bit in the EAV/SAV code is overwritten. It is possible
to use VBI in this timing mode as well.
In DVD record applications where the encoder is used with a
decoder, the VCR FF/RW sync control bit can be used for non-
standard input video, that is, in fast forward or rewind modes.
If CGMS is enabled and VBI is disabled, the CGMS data is
nevertheless available at the output.
In fast forward mode, the sync information at the start of a new
field in the incoming video usually occurs before the correct
number of lines/fields is reached. In rewind mode, this sync
signal usually occurs after the total number of lines/fields is
reached. Conventionally, this means that the output video has
corrupted field signals because one signal is generated by the
incoming video and another is generated when the internal
line/field counters reach the end of a field.
SD SUBCARRIER FREQUENCY REGISTERS
Subaddress 0x8C to Subaddress 0x8F
Four 8-bit registers are used to set up the subcarrier frequency.
The value of these registers is calculated using the following
equation:
Subcarrier Frequency Register =
When the VCR FF/RW sync control is enabled (Subaddress 0x82,
Bit 5), the line/field counters are updated according to the
Number of subcarrier periods in one video line
× 232
VSYNC
incoming
the incoming
signal and when the analog output matches
VSYNC
Number of 27 MHz clock cycles in one video line
signal.
where the sum is rounded to the nearest integer.
For example, in NTSC mode:
This control is available in all slave-timing modes except
Slave Mode 0.
227.5
1716
⎛
⎜
⎝
⎞
⎟
⎠
Subcarrier Register Value =
×
32 = 569408543
2
VERTICAL BLANKING INTERVAL
Subaddress 0x31, Bit 4; Subaddress 0x83, Bit 4
where:
The ADV739x is able to accept input data that contains vertical
blanking interval (VBI) data (such as CGMS, WSS, VITS) in
SD, ED, and HD modes.
Subcarrier Register Value = 569408543d = 0×21F07C1F
SD FSC Register 0: 0x1F
SD FSC Register 1: 0x7C
SD FSC Register 2: 0xF0
SD FSC Register 3: 0x21
If VBI is disabled (Subaddress 0x31, Bit 4 for ED/HD;
Subaddress 0x83, Bit 4 for SD), VBI data is not present at the
output and the entire VBI is blanked. These control bits are
valid in all master and slave timing modes.
For the SMPTE 293M (525p) standard, VBI data can be
inserted on Line 13 to Line 42 of each frame, or on Line 6 to
Lind 43 for the ITU-R BT.1358 (625p) standard.
Rev. 0 | Page 47 of 96
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