ADV7390/ADV7391/ADV7392/ADV7393
Programming the FSC
A 27 MHz clock signal must be provided on the CLKIN pin.
Embedded EAV/SAV timing codes or external horizontal and
The subcarrier frequency register value is divided into four FSC
registers as shown in the previous example. The four subcarrier
frequency registers must be updated sequentially, starting with
Subcarrier Frequency Register 0 and ending with Subcarrier
Frequency Register 3. The subcarrier frequency updates only
after the last subcarrier frequency register byte has been
received by the ADV739x.
HSYNC
vertical synchronization signals provided on the
VSYNC
and
pins can be used to synchronize the input pixel data.
All input configurations, output configurations, and features
available in NTSC and PAL modes are available in SD noninter-
laced mode.
For 240p/59.94 Hz input, the ADV739x should be configured for
NTSC operation and Subaddress 0x88, Bit 1 should be set to 1.
Typical FSC Values
Table 37 outlines the values that should be written to the
subcarrier frequency registers for NTSC and PAL B/D/G/H/I.
For 288p/50 Hz input, the ADV739x should be configured for
PAL operation and Subaddress 0x88, Bit 1 should be set to 1.
Table 37. Typical FSC Values
SD SQUARE PIXEL MODE
Subaddress
Description
NTSC
0x1F
0x7C
0xF0
0x21
PAL B/D/G/H/I
0xCB
0x8A
0x09
0x2A
Subaddress 0x82, Bit 4
0x8C
0x8D
0x8E
0x8F
FSC0
FSC1
FSC2
FSC3
The ADV739x can be used to operate in square pixel mode
(Subaddress 0x82, Bit 4). For NTSC operation, an input clock of
24.5454 MHz is required. Alternatively, for PAL operation, an
input clock of 29.5 MHz is required. The internal timing logic
adjusts accordingly for square pixel mode operation.
SD NONINTERLACED MODE
Subaddress 0x88, Bit 1
In square pixel mode, the timing diagrams shown in Figure 65
and Figure 66 apply.
The ADV739x supports a SD noninterlaced mode. Using this
mode, progressive inputs at twice the frame rate of NTSC and
PAL (240p/59.94 Hz and 288p/50 Hz, respectively) can be input
into the ADV739x. The SD noninterlaced mode can be enabled
using Subaddress 0x88, Bit 1.
ANALOG
VIDEO
EAV CODE
SAV CODE
C
b
C
r
C
b
8
0
0
0
F
F
F
F
A
B
A
B
A
B
8
0
0
0
C
r
F
F
0
0
0
0
X
Y
1
0
8
0
1
0
8
0
1
0
1
0
F
F
0
0
X
Y
C
b
C
r
Y
Y
Y
Y
Y
Y
INPUT PIXELS
ANCILLARY DATA
(HANC)
4 CLOCK
4 CLOCK
4 CLOCK
4 CLOCK
NTSC/PAL M SYSTEM
(525 LINES/60Hz)
272 CLOCK
1280 CLOCK
1536 CLOCK
PAL SYSTEM
(625 LINES/50Hz)
344 CLOCK
START OF ACTIVE
VIDEO LINE
END OF ACTIVE
VIDEO LINE
Figure 65. Square Pixel Mode EAV/SAV Embedded Timing
HSYNC
FIELD
PIXEL
DATA
Cr
Y
Cb
Y
PAL = 308 CLOCK CYCLES
NTSC = 236 CLOCK CYCLES
Figure 66. Square Pixel Mode Active Pixel Timing
Rev. 0 | Page 48 of 96
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