ADV7390/ADV7391/ADV7392/ADV7393
ENHANCED DEFINITION/HIGH DEFINITION
Subaddress 0x01, Bits[6:4] = 001 or 010
M
PEG2
ADV7392/
ADV7393
DECODER
CLKIN
YCrCb
ED or HD YCrCb data can be input in a 4:2:2 format over an
8-/10-bit DDR bus or a 16-bit SDR bus.
8
8
CrCb
Y
P[7:0]
The clock signal must be provided on the CLKIN pin. If
required, external synchronization signals can be provided on
INTERLACED TO
PROGRESSIVE
P[15:8]
HSYNC
codes are also supported.
VSYNC
the
and
pins. Embedded EAV/SAV timing
2
VSYNC
HSYNC
16-Bit 4:2:2 YCrCb Mode (SDR)
Figure 57. ED/HD-SDR Example Application
In 16-bit 4:2:2 YCrCb input mode, the Y pixel data is input on
Pin P15 to Pin P8, with P8 being the LSB.
MPEG2
ADV7392/
DECODER
The CrCb pixel data is input on Pin P7 to Pin P0, with P0
being the LSB.
ADV7393
CLKIN
YCrCb
8-/10-Bit 4:2:2 YCrCb Mode (DDR)
8/10
2
YCrCb
In 8-/10-bit DDR 4:2:2 YCrCb input mode, the Y pixel data is
input on Pin P15 to Pin P8/P6 upon either the rising or falling
edge of CLKIN. P8/P6 is the LSB.
P[15:8]/P[15:6]
INTERLACED TO
PROGRESSIVE
VSYNC
HSYNC
The CrCb pixel data is also input on Pin P15 to Pin P8/P6
upon the opposite edge of CLKIN. P8/P6 is the LSB.
Figure 58. ED/HD-DDR Example Application
10-bit mode is enabled using Subaddress 0x33, Bit 2. Whether
the Y data is clocked in upon the rising or falling edge of CLKIN
is determined by Subaddress 0x01, Bits[2:1] (see Figure 55 and
Figure 56).
ENHANCED DEFINITION (AT 54 MHz)
Subaddress 0x01, Bits[6:4] = 111
ED YCrCb data can be input in an interleaved 4:2:2 format on
an 8-/10-bit bus at a rate of 54 MHz.
A 54 MHz clock signal must be provided on the CLKIN pin.
Embedded EAV/SAV timing codes are supported. External
synchronization signals are not supported in this mode.
CLKIN
P[15:8]/
P]15:6]
3FF
00
00
X
Y
Cb0
Y0
Cr0
Y1
The interleaved pixel data is input on Pin P15 to Pin P8/P6,
with P8/P6 being the LSB.
NOTES
1. SUBADDRESS 0x01 [2:1] SHOULD BE SET TO 00 IN THIS CASE.
2. 10-BIT MODE IS ENABLED USING SUBADDRESS 0x33, BIT 2.
10-bit mode is enabled using Subaddress 0x33, Bit 2.
Figure 55. ED/HD-DDR Input Sequence (EAV/SAV)—Option A
CLKIN
CLKIN
P[15:8]/P[15:6]
NOTES
3FF
00
00
XY
Cb0
Y0
Cr0
Y1
P[15:8]/
P[15:P6]
3FF
00
00
XY
Y0
Cb0
Y1
Cr0
1. 10-BIT MODE IS ENABLED USING SUBADDRESS 0x33, BIT 2.
NOTES
Figure 59. ED (At 54 MHz) Input Sequence (EAV/SAV)
1. SUBADDRESS 0x01 [2:1] SHOULD BE SET TO 11 IN THIS CASE.
2. 10-BIT MODE IS ENABLED USING SUBADDRESS 0x33, BIT 2.
Figure 56. ED/HD-DDR Input Sequence (EAV/SAV)—Option B
MPEG2
DECODER
ADV7392/
ADV7393
54MHz
CLKIN
YCrCb
8/10
2
YCrCb
P[15:8]/P[15:6]
INTERLACED TO
PROGRESSIVE
VSYNC,
HSYNC
Figure 60. ED (At 54 MHz) Example Application
Rev. 0 | Page 43 of 96
ADI [ ADI ]
