ADV7390/ADV7391/ADV7392/ADV7393
ADV7392/ADV7393 INPUT CONFIGURATION
16-Bit 4:2:2 YCrCb Mode
The ADV7392/ADV7393 supports a number of different input
modes. The desired input mode is selected using Subaddress 0x01,
Bits[6:4]. The ADV7392/ADV7393 defaults to standard
definition (SD) mode upon power-up. Table 31 provides an
overview of all possible input configurations. Each input mode
is described in detail in this section.
Subaddress 0x87, Bit 7 = 0
Subaddress 0x88, Bits[4:3] = 01
In 16-bit 4:2:2 YCrCb input mode, the Y pixel data is input on
Pin P15 to Pin P8, with P8 being the LSB.
The CrCb pixel data is input on Pin P7 to Pin P0, with P0 being
the LSB.
STANDARD DEFINITION
Subaddress 0x01, Bits[6:4] = 000
The pixel data is updated at half the rate of the clock, that is, at a
rate of 13.5 MHz (see Figure 3).
SD YCrCb data can be input in 4:2:2 format over an 8-, 10-, or 16-
bit bus. SD RGB data can be input in 4:4:4 format over a 16-bit bus.
16-Bit 4:4:4 RGB Mode
A 27 MHz clock signal must be provided on the CLKIN pin. If
required, external synchronization signals can be provided on
Subaddress 0x87, Bit 7 = 1
In 16-bit 4:4:4 RGB input mode, the red pixel data is input on
Pin P4 to Pin P0, the green pixel data is input on Pin P10 to
Pin P5, and the blue pixel data is input on Pin P15 to Pin P11.
P0, P5, and P11 are the respective bus LSBs.
HSYNC
VSYNC
the
and
pins. Embedded EAV/SAV timing
codes are also supported in 8-bit and 10-bit modes.
8-Bit 4:2:2 YCrCb Mode
Subaddress 0x87, Bit 7 = 0
Subaddress 0x88, Bits[4:3] = 00
The pixel data is updated at half the rate of the clock, that is, at a
rate of 13.5 MHz (see Figure 4).
In 8-bit 4:2:2 YCrCb input mode, the interleaved pixel data is
input on Pin P15 to Pin P8, with P8 being the LSB. The ITU-R
BT.601/656 input standard is supported.
ADV7392/
ADV7393
2
VSYNC,
MPEG2
HSYNC
DECODER
10-Bit 4:2:2 YCrCb Mode
27MHz
CLKIN
Subaddress 0x87, Bit 7 = 0
Subaddress 0x88, Bits[4:3] = 10
8/10
YCrCb
P[15:8]/P[15:6]
In 10-bit 4:2:2 YCrCb input mode, the interleaved pixel data is
input on Pin P15 to Pin P6, with P6 being the LSB. The ITU-R
BT.601/656 input standard is supported.
Figure 54. SD Example Application
Table 31. ADV7392/ADV7393 Input Configuration
1
Input Mode
P15
P14
P13
P12
P11
P10
P9 P8 P7 P6 P5 P4 P3 P2 P1 P0
2
000
SD
SD RGB Input Enable (0x87[7]) = 0
YCrCb
SD RGB Input Enable (0x87[7]) = 1
8-Bit
YCrCb
10-Bit
16-Bit
3
Y
CrCb
16-Bit3
B
G
R
001
010
ED/HD-SDR (16-Bit)
Y
CrCb
4
ED/HD-DDR
ED/HD Input Format (0x33[2]) = 0
ED/HD Input Format (0x33[2]) = 1
8-Bit
YCrCb
10-Bit
ED (At 54 MHz)
8-Bit
YCrCb
111
ED/HD Input Format (0x33[2]) = 0
YCrCb
ED/HD Input Format (0x33[2]) = 1
10-Bit
YCrCb
1 The input mode is determined by Subaddress 0x01, Bits[6:4].
2 In SD mode, the width of the input data is determined by Subaddress 0x88, Bits[4:3].
3 External synchronization signals must be used in this input mode. Embedded EAV/SAV timing codes are not supported.
4 ED = enhanced definition = 525p and 625p.
Rev. 0 | Page 42 of 96
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