ADV7390/ADV7391/ADV7392/ADV7393
ADV7390/ADV7391 INPUT CONFIGURATION
The ADV7390/ADV7391 supports a number of different input
modes. The desired input mode is selected using Subaddress 0x01,
Bits[6:4]. The ADV7390/ADV7391 defaults to standard
definition (SD) mode upon power-up. Table 30 provides an
overview of all possible input configurations. Each input mode
is described in detail in this section.
The CrCb pixel data is also input on Pin P7 to Pin P0
upon the opposite edge of CLKIN. P0 is the LSB.
Whether the Y data is clocked in upon the rising or falling edge
of CLKIN is determined by Subaddress 0x01, Bits[2:1] (see
Figure 50 and Figure 51).
CLKIN
Table 30. ADV7390/ADV7391 Input Configuration
Input Mode
P7 P6 P5 P4 P2 P2 P1 P0
P[7:0]
3FF
00
00
XY
Cb0
Y0
Cr0
Y1
000 SD
010 ED/HD-DDR
111 ED (at 54 MHz)
YCrCb
YCrCb
YCrCb
NOTES
1. SUBADDRESS 0x01 [2:1] SHOULD BE SET TO 00 IN THIS CASE.
Figure 50. ED/HD-DDR Input Sequence (EAV/SAV)—Option A
STANDARD DEFINITION
Subaddress 0x01, Bits[6:4] = 000
CLKIN
SD YCrCb data can be input in an interleaved 4:2:2 format over
an 8-bit bus rate of 27 MHz.
P[7:0]
3FF
00
00
XY
Y0
Cb0
Y1
Cr0
A 27 MHz clock signal must be provided on the CLKIN pin. If
required, external synchronization signals can be provided on
NOTES
1. SUBADDRESS 0x01 [2:1] SHOULD BE SET TO 11 IN THIS CASE.
Figure 51. ED/HD-DDR Input Sequence (EAV/SAV)—Option B
HSYNC
VSYNC
the
and
pins. Embedded EAV/SAV timing
codes are also supported. The ITU-R BT.601/656 input standard
is supported.
MPEG2
DECODER
ADV7390/
ADV7391
CLKIN
YCrCb
The interleaved pixel data is input on Pin P7 to Pin P0, with P0
being the LSB.
8
YCrCb
P[7:0]
ADV7390/
ADV7391
INTERLACED TO
PROGRESSIVE
2
VSYNC,
MPEG2
HSYNC
2
DECODER
VSYNC,
HSYNC
27MHz
CLKIN
Figure 52. ED/HD-DDR Example Application
8
YCrCb
ENHANCED DEFINITION (AT 54 MHz)
P[7:0]
Subaddress 0x01, Bits[6:4] = 111
Figure 49. SD Example Application
ED YCrCb data can be input in an interleaved 4:2:2 format over
an 8-bit bus rate of 54 MHz.
ENHANCED DEFINITION/HIGH DEFINITION
Subaddress 0x01, Bits[6:4] = 010
A 54 MHz clock signal must be provided on the CLKIN pin.
Embedded EAV/SAV timing codes are supported. External
synchronization signals are not supported in this mode.
ED or HD YCrCb data can be input in an interleaved 4:2:2
format over an 8-bit DDR bus.
The clock signal must be provided on the CLKIN pin. If
required, external synchronization signals can be provided on
The interleaved pixel data is input on Pin P7 to Pin P0, with P0
being the LSB.
HSYNC
VSYNC
the
and
pins. Embedded EAV/SAV timing
CLKIN
codes are also supported.
8-Bit 4:2:2 ED/HD YCrCb Mode (DDR)
P[7:0]
3FF
00
00
XY
Cb0
Y0
Cr0
Y1
In 8-bit DDR 4:2:2 YCrCb input mode, the Y pixel data is input
on Pin P7 to Pin P0 upon either the rising or falling edge of
CLKIN. P0 is the LSB.
Figure 53. ED (At 54 MHz) Input Sequence (EAV/SAV)
Rev. 0 | Page 41 of 96
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