ADV7390/ADV7391/ADV7392/ADV7393
Table 26. Register 0x8A to Register 0x98
SR7 to
Bit Number
Reset
Value
0x08
SR0
Register
Bit Description
7
6
5
4
3
2
1
0
0
1
Register Setting
Slave mode
Master mode
Mode 0
Mode 1
Mode 2
0x8A
SD Timing Register 0
SD Slave/Master Mode.
SD Timing Mode.
0
0
1
1
0
1
0
1
Mode 3
Reserved.
1
SD Luma Delay.
0
0
1
1
0
1
0
1
No delay
2 clock cycles
4 clock cycles
6 clock cycles
−40 IRE
SD Minimum Luma Value.
SD Timing Reset.
0
1
−7.5 IRE
x
A low-high-low transition
resets the internal SD
timing counters
0x8B
SD Timing Register 1
Note: Applicable in
master modes only,
that is, Subaddress
0x8A, Bit 0 = 1.
HSYNC
0
0
1
1
0
1
0
1
ta = 1 clock cycle
ta = 4 clock cycles
ta = 16 clock cycles
ta = 128 clock cycles
tb = 0 clock cycles
tb = 4 clock cycles
tb = 8 clock cycles
tb = 18 clock cycles
tc = tb
0x00
SD
SD
SD
Width.
HSYNC VSYNC
to
0
0
1
1
0
1
0
1
Delay.
Rising
HSYNC VSYNC
to
Edge Delay (Mode 1 Only).
x
x
0
0
1
1
0
1
0
1
0
1
tc = tb + 32 μs
VSYNC
1 clock cycle
4 clock cycles
16 clock cycles
128 clock cycles
0 clock cycles
1 clock cycle
2 clock cycles
3 clock cycles
Width (Mode 2 Only).
HSYNC
0
0
1
1
x
0
1
0
1
x
to Pixel Data Adjust.
0x8C
0x8D
0x8E
0x8F
SD FSC Register 01
SD FSC Register 11
SD FSC Register 21
SD FSC Register 31
SD FSC Phase
Subcarrier Frequency Bits[7:0]
Subcarrier Frequency Bits[15:8]
Subcarrier Frequency Bits[23:16]
Subcarrier Frequency Bits[31:24]
Subcarrier Phase Bits[9:2]
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Subcarrier Frequency
Bits[7:0]
0x1F
0x7C
0xF0
0x21
x
x
x
x
x
x
Subcarrier Frequency
Bits[15:8]
Subcarrier Frequency
Bits[23:16]
Subcarrier Frequency
Bits[31:24]
0x90
0x91
0x92
0x93
0x94
0x95
0x96
0x97
0x98
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Subcarrier Phase Bits[9:2]
Extended Data Bits[7:0]
0x00
0x00
SD Closed Captioning Extended Data on Even Fields.
SD Closed Captioning Extended Data on Even Fields.
SD Closed Captioning Data on Odd Fields.
Extended Data Bits[15:8]. 0x00
Data Bits[7:0]
Data Bits[15:8]
0x00
0x00
SD Closed Captioning Data on Odd Fields.
SD Pedestal Register 0
SD Pedestal Register 1
SD Pedestal Register 2
SD Pedestal Register 3
Pedestal on Odd Fields.
Pedestal on Odd Fields.
Pedestal on Even Fields.
Pedestal on Even Fields.
17 16 15 14 13 12 11 10 Setting any of these bits 0x00
to 1 disables pedestal
25 24 23 22 21 20 19 18
17 16 15 14 13 12 11 10
25 24 23 22 21 20 19 18
0x00
0x00
0x00
on the line number
indicated by the bit
settings
1 SD subcarrier frequency registers default to NTSC subcarrier frequency values.
Rev. 0 | Page 37 of 96
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