ADV7390/ADV7391/ADV7392/ADV7393
Table 24. Register 0x84 to Register 0x87
SR7 to
Bit Number
Reset
Value
0x00
SR0
Register
Bit Description
VSYNC
7
6
5
4
3
2
1
0
0
1
Register Setting
0x84
SD Mode
Register 4
Disabled
SD
-3H.
VSYNC
VSYNC
= 2.5 lines (PAL),
= 3 lines (NTSC)
SD SFL/SCR/TR Mode Select.
0
0
1
1
0
1
0
1
Disabled
Subcarrier reset mode enabled
Timing reset mode enabled
SFL mode enabled
720 pixels
710 (NTSC), 702 (PAL)
Chroma enabled
Chroma disabled
Enabled
SD Active Video Length.
SD Chroma.
0
1
0
1
SD Burst.
0
1
Disabled
SD Color Bars.
0
1
Disabled
Enabled
SD Luma/Chroma Swap.
0
1
DAC 2 = luma, DAC 3 = chroma
DAC 2 = chroma, DAC 3 = luma
5.17 ꢀs
5.31 ꢀs
5.59 ꢀs (must be set for
Macrovision compliance)
0x86
SD Mode
Register 5
NTSC Color Subcarrier Adjust (Delay from
the falling edge of output HSYNC pulse to
start of color burst).
0
0
1
0
1
0
0x02
1
1
Reserved
Reserved.
0
SD EIA/CEA-861B Synchronization
Compliance.
0
1
Disabled
Enabled
Reserved.
0
0
SD Horizontal/Vertical Counter Mode.1
0
1
Update field/line counter
Field/line counter free running
Normal
Color reversal enabled
Disabled
SD RGB Color Swap.2
SD PrPb Scale.
0
1
0x87
SD Mode
Register 6
0
1
0x00
Enabled
SD Y Scale.
0
1
Disabled
Enabled
SD Hue Adjust.
0
1
Disabled
Enabled
SD Brightness.
0
1
Disabled
Enabled
SD Luma SSAF Gain.
SD Input Standard Auto Detection.
0
1
Disabled
Enabled
0
1
Disabled
Enabled
Reserved.
SD RGB Input Enable.2
0
0 must be written to this bit
SD YCrCb input
SD RGB input
0
1
1 When set to 0, the horizontal/vertical counters automatically wrap around at the end of the line/field/frame of the selected standard. When set to 1, the
horizontal/vertical counters are free running and wrap around when external sync signals indicate to do so.
2 Available on the ADV7392/ADV7393 (40-pin devices) only.
Rev. 0 | Page 35 of 96
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