ADV7390/ADV7391/ADV7392/ADV7393
Table 25. Register 0x88 to Register 0x89
SR7 to
Bit Number
Reset
Value
0x00
SR0
Register
Bit Description
Reserved.
7
6
5
4
3
2
1
0
Register Setting
0x88
SD Mode
Register 7
0
SD Noninterlaced Mode.
0
1
Disabled
Enabled
SD Double Buffering.
SD Input Format.
0
1
Disabled
Enabled
0
0
1
1
0
1
0
1
8-bit input
16-bit input1
10-bit input1
Reserved
SD Digital Noise Reduction.
SD Gamma Correction Enable.
SD Gamma Correction Curve Select.
SD Undershoot Limiter.
0
1
Disabled
Enabled
0
1
Disabled
Enabled
0
1
Gamma Correction Curve A
Gamma Correction Curve B
Disabled
−11 IRE
−6 IRE
0x89
SD Mode
Register 8
0
0
1
1
0
1
0
1
0x00
−1.5 IRE
Reserved.
0
0 must be written to this bit
Disabled
Enabled
SD Black Burst Output on DAC Luma.
0
1
SD Chroma Delay.
0
0
1
1
0
1
0
1
Disabled
4 clock cycles
8 clock cycles
Reserved
Reserved.
0
0
0 must be written to these bits
1 Available on the ADV7392/ADV7393 (40-pin devices) only.
Rev. 0 | Page 36 of 96
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