ADV7180
Address
Reset
Dec Hex Register Name
154 9A CCAP 2
RW 7
6
5
4
3
2
1
0
Value
(Hex)
R
CCAP2[7]
CCAP2[6]
LB_LCT[6]
LB_LCM[6]
LB_LCB[6]
CCAP2[5]
LB_LCT[5]
LB_LCM[5]
LB_LCB[5]
CCAP2[4]
LB_LCT[4]
LB_LCM[4]
LB_LCB[4]
CCAP2[3]
LB_LCT[3]
LB_LCM[3]
LB_LCB[3]
CCAP2[2]
LB_LCT[2]
LB_LCM[2]
LB_LCB[2]
CRC_ENABLE
MUX0[2]
MUX2[2]
LB_TH[2]
LB_EL[2]
CCAP2[1]
LB_LCT[1]
LB_LCM[1]
LB_LCB[1]
CCAP2[0]
LB_LCT[0]
LB_LCM[0]
LB_LCB[0]
–
–
–
–
–
–
–
–
155 9B Letterbox 1
R
LB_LCT[7]
LB_LCM[7]
LB_LCB[7]
156 9C Letterbox 2
R
157 9D Letterbox 3
R
178 B2 CRC
W
00011100 1C
xxxxxxxx 00
0xxxxxxx 00
10101100 AC
01001100 4C
195 C3 ADC Switch 1
196 C4 ADC Switch 2
220 DC Letterbox Control 1
221 DD Letterbox Control 2
222 DE ST Noise Readback 1
223 DF ST Noise Readback 2
224 E0 Reserved
RW MUX1[3]
MUX1[2]
MUX1[1]
LB_SL[1]
MUX1[0]
MUX0[3]
MUX2[3]
LB_TH[3]
LB_EL[3]
MUX0[1]
MUX2[1]
LB_TH[1]
LB_EL[1]
MUX0[0]
MUX2[0]
LB_TH[0]
LB_EL[0]
RW MAN_MUX_EN
RW
LB_TH[4]
LB_SL[0]
RW LB_SL[3]
R
LB_SL.2
ST_NOISE_VLD ST_NOISE[10]
ST_NOISE[3] ST_NOISE[2]
ST_NOISE[9] ST_NOISE[8]
ST_NOISE[1] ST_NOISE[0]
–
–
–
–
R
ST_NOISE[7]
ST_NOISE.6
ST_NOISE[5] ST_NOISE[4]
225 E1 SD Offset Cb
226 E2 SD Offset Cr
227 E3 SD Saturation Cb
228 E4 SD Saturation Cr
229 E5 NTSC V Bit Begin
230 E6 NTSC V Bit End
231 E7 NTSC F Bit Toggle
232 E8 PAL V Bit Begin
233 E9 PAL V Bit End
234 EA PAL F Bit Toggle
235 EB Vblank Control 1
236 EC Vblank Control 2
243 F3 AFE_CONTROL 1
RW SD_OFF_CB[7] SD_OFF_CB[6] SD_OFF_CB[5] SD_OFF_CB[4] SD_OFF_CB[3] SD_OFF_CB[2]
RW SD_OFF_CR[7] SD_OFF_CR[6] SD_OFF_CR[5] SD_OFF_CR[4] SD_OFF_CR[3] SD_OFF_CR[2]
RW SD_SAT_CB[7] SD_SAT_CB[6] SD_SAT_CB[5] SD_SAT_CB[4] SD_SAT_CB[3] SD_SAT_CB[2]
RW SD_SAT_CR[7] SD_SAT_CR[6] SD_SAT_CR[5] SD_SAT_CR[4] SD_SAT_CR[3] SD_SAT_CR[2]
SD_OFF_CB[1] SD_OFF_CB[0]
SD_OFF_CR[1] SD_OFF_CR[0]
SD_SAT_CB[1] SD_SAT_CB[0]
SD_SAT_CR[1] SD_SAT_CR[0]
10000000 80
10000000 80
10000000 80
10000000 80
00100101 25
00000100 04
01100011 63
01100101 65
00010100 14
01100011 63
01010101 55
01010101 55
00000000 00
RW NVBEGDELO
RW NVENDDELO
RW NFTOGDELO
RW PVBEGDELO
RW PVENDDELO
RW PFTOGDELO
NVBEGDELE
NVENDDELE
NFTOGDELE
PVBEGDELE
PVENDDELE
PFTOGDELE
NVBEGSIGN NVBEG[4]
NVENDSIGN NVEND[4]
NFTOGSIGN NFTOG[4]
NVBEG[3]
NVEND[3]
NFTOG[3]
PVBEG[3]
PVEND[3]
PFTOG[3]
PVBIOLCM.1
NVBEG[2]
NVEND[2]
NFTOG[2]
PVBEG[2]
PVEND[2]
PFTOG[2]
PVBIOLCM.0
NVBEG[1]
NVEND[1]
NFTOG[1]
PVBEG[1]
PVEND[1]
PFTOG[1]
PVBIELCM.1
NVBEG[0]
NVEND[0]
NFTOG[0]
PVBEG[0]
PVEND[0]
PFTOG[0]
PVBIELCM.0
PVBEGSIGN
PVENDSIGN PVEND[4]
PFTOGSIGN PFTOG[4]
PVBEG[4]
RW NVBIOLCM[1] NVBIOLCM[0] NVBIELCM[1] NVBIELCM[0]
RW NVBIOCCM[1] NVBIOCCM[0] NVBIECCM[1] NVBIECCM[0] PVBIOCCM.1 PVBIOCCM.0
PVBIECCM.1 PVBIECCM.0
AA_FILT_EN[1] AA_FILT_EN[0]
RW
AA_FILT_
AA_FILT_EN[2]
MAN_OVR
244 F4 Drive Strength
248 F8 IF Comp Control
249 F9 VS Mode Control
RW
RW
RW
DR_STR[1]
DR_STR[0]
DR_STR_C[1] DR_STR_C[0]
IFFILTSEL[2]
DR_STR_S[1] DR_STR_S[0]
xx010101 15
00000000 00
00000011 03
IFFILTSEL[1]
IFFILTSEL[0]
VS_COAST_
MODE[1]
VS_COAST_
MODE[0]
EXTEND_VS_ EXTEND_VS_
MIN_FREQ
MAX_FREQ
251 FB Peaking Control
252 FC Coring Threshold
RW PEAKING_
GAIN[7]
PEAKING_
GAIN[6]
PEAKING_
GAIN[5]
PEAKING_
GAIN[4]
PEAKING_
GAIN[3]
PEAKING_
GAIN[2]
PEAKING_
GAIN[1]
PEAKING_
GAIN[0]
01000000 40
00000100 04
RW DNR_TH2[7]
DNR_TH2[6]
DNR_TH2[5] DNR_TH2[4]
DNR_TH2[3]
DNR_TH2[2]
DNR_TH2[1] DNR_TH2[0]
1 This feature applies to the ADV7180BCPZ 40-lead only because VS or field are shared on a single pin (Pin 37).
2 This feature applies to the ADV7180BSTZ 64-lead only.
Table 102. Interrupt System Register Map Details1
Address
Reset
Dec
Hex
Register Name
R/W
7
6
5
4
3
2
1
0
Value
(Hex)
64
40
Interrupt
Config. 1
RW
INTRQ_DUR_
SEL[1]
INTRQ_DUR_
SEL[0]
MV_INTRQ_
SEL[1]
MV_INTRQ_
SEL[0]
MPU_STIM_
INTRQ
INTRQ_OP_
SEL[1]
INTRQ_OP_SE
L[0]
0001x000
10
66
67
68
69
70
71
72
42
43
44
45
46
47
48
Interrupt
Status 1
R
MV_PS_CS_Q
SD_FR_
CHNG_Q
SD_UNLOCK
_Q
SD_LOCK_Q
–
–
Interrupt Clear 1
W
RW
R
MV_PS_CS_
CLR
SD_FR_
CHNG_CLR
SD_UNLOCK_
CLR
SD_LOCK_
CLR
x0000000
x0000000
–
00
00
–
Interrupt
Mask 1
MV_PS_CS_
MSKB
SD_FR_
CHNG_MSKB
SD_UNLOCK_
MSKB
SD_LOCK_
MSKB
Raw
Status 1
MPU_STIM_I
NTRQ
EVEN_FIELD
CCAPD
Interrupt
Status 2
R
MPU_STIM_
INTRQ_Q
SD_FIELD_
CHNGD_Q
GEMD_Q
CCAPD_Q
CCAPD_CLR
–
–
Interrupt Clear 2
W
RW
MPU_STIM_
INTRQ_CLR
SD_FIELD_
CHNGD_CLR
GEMD_CLR
GEMD_MSKB
0xx00000
0xx00000
00
00
Interrupt
Mask 2
MPU_STIM_
INTRQ_MSKB
SD_FIELD_
CHNGD_MSK
B
CCAPD_
MSKB
73
74
75
76
78
49
4A
4B
4C
4E
Raw
Status 2
R
SCM_LOCK
SD_H_LOCK
SD_V_LOCK
SD_OP_50Hz
–
–
Interrupt
Status 3
R
PAL_SW_LK_
CHNG_Q
SCM_LOCK_
CHNG_Q
SD_AD_
CHNG_Q
SD_H_LOCK_
CHNG_Q
SD_V_LOCK_
CHNG_Q
SD_OP_
CHNG_Q
–
–
Interrupt Clear 3
W
RW
R
PAL_SW_LK_
CHNG_CLR
SCM_LOCK_
CHNG_CLR
SD_AD_
CHNG_CLR
SD_H_LOCK_
CHNG_CLR
SD_V_LOCK_
CHNG_CLR
SD_OP_
CHNG_CLR
xx000000
xx000000
–
00
00
–
Interrupt
Mask 3
PAL_SW_LK_
CHNG_MSKB
SCM_LOCK_
CHNG_MSKB
SD_AD_
CHNG_MSKB
SD_H_LOCK_
CHNG_MSKB
SD_V_LOCK_
CHNG_MSKB
SD_OP_
CHNG_MSKB
Interrupt
Status 4
VDP_VITC_Q
VDP_GS_
VPS_PDC_
UTC_CHNG_
Q
VDP_CGMS_
WSS_
CHNGD_Q
VDP_CCAPD_
Q
79
4F
Interrupt Clear 4
W
VDP_VITC_
CLR
VDP_GS_
VPS_PDC_
UTC_CHNG_
CLR
VDP_CGMS_
WSS_CHNGD
_CLR
VDP_CCAPD_
CLR
00x0x0x0
00
Rev. A | Page 77 of 112
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