ADV7180
ANALOG_INPUT_1
Y
THE SUGGESTED INPUT ARRANGEMENT
IS AS SEEN ON THE EVAL BOARD AND IS
DIRECTLY SUPPORTED BY INSEL.
0.1µF
A
A
A
A
A
A
1
2
3
4
5
6
IN
IN
IN
IN
IN
IN
36ꢀ
39ꢀ
D
_1.8V
D
_1.8V
VDD
VDD
ANALOG_INPUT_2
CVBS
0.1µF
10nF
0.1µF
0.1µF
10nF
36ꢀ
39ꢀ
D
_3.3V
0.1µF
ANALOG_INPUT_3
YC_Y
A
_1.8V
10nF
VDDIO
VDD
0.1µF
0.1µF
36ꢀ
D
_3.3V
P
_1.8V
39ꢀ
VDDIO
VDD
10nF
ANALOG_INPUT_4
Cr
10nF
0.1µF
0.1µF
0.1µF
10nF
36ꢀ
39ꢀ
P[0:7]
ANALOG_INPUT_5
Cb
0.1µF
8-BIT
OUTPUT MODE
16-BIT
OUTPUT MODE
35
36
46
47
48
49
DATA BUS
P[0:7]
A
A
A
A
A
A
1
A
1
2
3
4
5
6
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
26
25
19
18
17
16
15
14
P0
P1
P2
P3
P4
P5
P6
P7
P0
P1
P2
P3
P4
P5
P6
P7
36ꢀ
---
Y
39ꢀ
2
3
4
5
6
A
A
A
A
A
P[8:15]
656/601 YCbCr
CbCr
ANALOG_INPUT_6
YC_C
0.1µF
P[8:15]
36ꢀ
39ꢀ
ADV7180BSTZ
8
7
6
5
62
61
60
59
P8
P9
LQFP–64
P8
P9
P10
P11
P12
P13
P14
P15
P10
P11
P12
P13
P14
P15
KEEP VREFN AND VREFP CAPS AS CLOSE AS
POSSIBLE TO THE ADV7180 AND ON THE SAME
SIDE OF THE PCB AS THE ADV7180.
39
38
VREFN
VREFP
0.1µF
0.1µF
1
INTRQ
INT
55
56
12
13
GPO3
GPO2
GPO1
GPO0
GPO3
GPO2
GPO1
GPO0
DO NOT STUFF C19
0.1µF
22
21
XTAL
63
64
2
47pF
FIELD
VS
FIELD
*
28.63636MHz
1Mꢀ
VSYNC
HS
HS
XTAL1
RESET
47pF
9
SFL
SFL
P
_1.8V
VDD
27, 28, 33,
41, 42, 44,
45, 50
51
29
EXTERNAL
LOOP FILTER
RESET
NC
PWRDWN
POWER_DOWN
10nF
30
ELPF
D
_3.3V
VDDIO
82nF
4kꢀ
52
1.69kꢀ
ALSB
2
2
KEEP CLOSE TO THE ADV7180 AND ON
THE SAME SIDE OF PCB AS THE ADV7180.
TIE HI: I C ADDRESS = 42
TIE LOW: I C ADDRESS = 40
20
LLC
LLC
33ꢀ
54
53
SCLK
SCLK
SDA
SDATA
33ꢀ
*REFER TO ANALOG DEVICES
CRYSTAL APPLICATION NOTE
FOR PROPER CAPACITOR LOADING.
NC = NO CONNECT
Figure 54. ADV7180 LQFP-64 Typical Connection Diagram
Rev. A | Page 110 of 112
ADI [ ADI ]
