Data Sheet
ADV7180
FIELD 1
1
622
623 624
2
3
4
5
6
7
8
9
10
11
23
24
625
OUTPUT
VIDEO
HS
OUTPUT
VS
OUTPUT
PVBEG[4:0] = 0x01
PVEND[4:0] = 0x04
FIELD
OUTPUT
PFTOG[4:0] = 0x06
FIELD 2
314
310
311
312
315
316
317
318
319
320
321
322
323
336
337
313
OUTPUT
VIDEO
HS
OUTPUT
VS
OUTPUT
PVBEG[4:0] = 0x01
PVEND[4:0] = 0x04
FIELD
OUTPUT
PFTOG[4:0] = 0x06
Figure 42. PAL Typical VS/FIELD Positions Using the Register Writes Shown in Table 66
PVBEG[4:0], PAL VSYNC Begin, Address 0xE8[4:0]
Table 66. User Settings for PAL (See Figure 42)
The default value of PVBEG is 00101, indicating the PAL VSYNC
begin position. For all NTSC/PAL VSYNC timing controls, the
V bit in the AV code and the VSYNC signal on the VS pin are
modified.
Register
0x31
0x32
0x33
0x34
0x35
0x36
0x37
0xE8
0xE9
0xEA
Register Name
VS/FIELD Control 1
VS/FIELD Control 2
VS/FIELD Control 3
HS Position Control 1
HS Position Control 2
HS Position Control 3
Polarity
Write
0x1A
0x81
0x84
0x00
0x00
0x7D
0xA1
0x41
0x84
0x06
1
PVBEGSIGN
0
ADVANCE BEGIN OF
VSYNC BY PVBEG[4:0]
DELAY BEGIN OF
VSYNC BY PVBEG[4:0]
PAL V bit begin
NOT VALID FOR USER
PROGRAMMING
PAL V bit end
PAL F bit toggle
ODD FIELD?
YES
NO
PVBEGDELO, PAL VSYNC Begin Delay on Odd Field,
Address 0xE8[7]
PVBEGDELO
1
PVBEGDELE
1
When PVBEGDELO is 0 (default), there is no delay.
0
0
Setting PVBEGDELO to 1 delays VSYNC going high on an odd
field by a line relative to PVBEG.
ADDITIONAL
DELAY BY
1 LINE
ADDITIONAL
DELAY BY
1 LINE
PVBEGDELE, PAL VSYNC Begin Delay on Even Field,
Address 0xE8[6]
When PVBEGDELE is 0, there is no delay.
VSBHO
1
VSBHE
1
Setting PVBEGDELE to 1 (default) delays VSYNC going high
on an even field by a line relative to PVBEG.
0
0
PVBEGSIGN, PAL VSYNC Begin Sign, Address 0xE8[5]
ADVANCE BY
0.5 LINE
ADVANCE BY
0.5 LINE
Setting PVBEGSIGN to 0 delays the beginning of VSYNC. Set
for user manual programming.
Setting PVBEGSIGN to 1 (default) advances the beginning of
VSYNC (not recommended for user programming).
VSYNC BEGIN
Figure 43. PAL VSYNC Begin
Rev. G | Page 51 of 120
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