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ADV7180KST48Z-RL 参数 Datasheet PDF下载

ADV7180KST48Z-RL图片预览
型号: ADV7180KST48Z-RL
PDF下载: 下载PDF文件 查看货源
内容描述: 10位, 4A ?过采样SDTV视频解码器 [10-Bit, 4× Oversampling SDTV Video Decoder]
分类和应用: 解码器电视
文件页数/大小: 120 页 / 2118 K
品牌: ADI [ ADI ]
 浏览型号ADV7180KST48Z-RL的Datasheet PDF文件第48页浏览型号ADV7180KST48Z-RL的Datasheet PDF文件第49页浏览型号ADV7180KST48Z-RL的Datasheet PDF文件第50页浏览型号ADV7180KST48Z-RL的Datasheet PDF文件第51页浏览型号ADV7180KST48Z-RL的Datasheet PDF文件第53页浏览型号ADV7180KST48Z-RL的Datasheet PDF文件第54页浏览型号ADV7180KST48Z-RL的Datasheet PDF文件第55页浏览型号ADV7180KST48Z-RL的Datasheet PDF文件第56页  
ADV7180  
Data Sheet  
PFTOGDELO, PAL Field Toggle Delay on Odd Field,  
Address 0xEA[7]  
1
PVENDSIGN  
0
When PFTOGDELO is 0 (default), there is no delay.  
ADVANCE END OF  
DELAY END OF VSYNC  
BY PVEND[4:0]  
VSYNC BY PVEND[4:0]  
Setting PFTOGDELO to 1 delays the F toggle/transition on an  
odd field by a line relative to PFTOG.  
NOT VALID FOR USER  
PROGRAMMING  
PFTOGDELE, PAL Field Toggle Delay on Even Field,  
Address 0xEA[6]  
ODD FIELD?  
YES  
NO  
When PFTOGDELE is 0, there is no delay.  
Setting PFTOGDELE to 1 (default) delays the F toggle/transition  
on an even field by a line relative to PFTOG.  
PVENDDELO  
1
PVENDDELE  
1
PFTOGSIGN, PAL Field Toggle Sign, Address 0xEA[5]  
0
0
Setting PFTOGSIGN to 0 delays the field transition. Set for user  
manual programming.  
ADDITIONAL  
DELAY BY  
1 LINE  
ADDITIONAL  
DELAY BY  
1 LINE  
Setting PFTOGSIGN to 1 (default) advances the field transition  
(not recommended for user programming).  
PFTOG, PAL Field Toggle, Address 0xEA[4:0]  
VSEHO  
1
VSEHE  
1
The default value of PFTOG is 00011, indicating the PAL field  
toggle position.  
0
0
For all NTSC/PAL field timing controls, the F bit in the AV  
code and the field signal on the FIELD pin are modified.  
ADVANCE BY  
0.5 LINE  
ADVANCE BY  
0.5 LINE  
1
PFTOGSIGN  
0
VSYNC END  
ADVANCE TOGGLE OF  
FIELD BY PFTOG[4:0]  
DELAY TOGGLE OF  
FIELD BY PFTOG[4:0]  
Figure 44. PAL VSYNC End  
PVENDDELO, PAL VSYNC End Delay on Odd Field,  
Address 0xE9[7]  
NOT VALID FOR USER  
PROGRAMMING  
ODD FIELD?  
When PVENDDELO is 0 (default), there is no delay.  
YES  
NO  
Setting PVENDDELO to 1 delays VSYNC going low on an odd  
field by a line relative to PVEND.  
PFTOGDELO  
1
PFTOGDELE  
1
PVENDDELE, PAL VSYNC End Delay on Even Field,  
Address 0xE9[6]  
0
0
When PVENDDELE is 0 (default), there is no delay.  
ADDITIONAL  
DELAY BY  
1 LINE  
ADDITIONAL  
DELAY BY  
1 LINE  
Setting PVENDDELE to 1 delays VSYNC going low on an even  
field by a line relative to PVEND.  
PVENDSIGN, PAL VSYNC End Sign, Address 0xE9[5]  
Setting PVENDSIGN to 0 (default) delays the end of VSYNC  
(set for user manual programming).  
FIELD  
TOGGLE  
Figure 45. PAL F Toggle  
Setting PVENDSIGN to 1 advances the end of VSYNC (not  
recommended for user programming).  
PVEND[4:0], PAL VSYNC End, Address 0xE9[4:0]  
The default value of PVEND is 10100, indicating the PAL  
VSYNC end position.  
For all NTSC/PAL VSYNC timing controls, both the V bit in  
the AV code and the VSYNC signal on the VS pin are modified.  
Rev. G | Page 52 of 120  
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