Data Sheet
ADV7180
VS and FIELD Configuration
HVSTIM, Horizontal VS Timing, Address 0x31[3]
The following controls allow the user to configure the behavior
of the VS and FIELD output pins, as well as the generation of
embedded AV codes.
The HVSTIM bit allows the user to select where the VS signal is
asserted within a line of video. Some interface circuitry may require
VS to go low while HS is low.
The 64-lead LQFP has separate VS and FIELD pins. The 48-lead
LQFP, 40-lead LFCSP, and 32-lead LFCSP do not have separate
VS and FIELD pins but can output either VS or FIELD on Pin 45
(48-lead LQFP), Pin 37 (40-lead LFCSP), or Pin 31 (32-lead
LFCSP), which is the VS/FIELD pin.
When HVSTIM is 0 (default), the start of the line is relative to HSE.
When HVSTIM is 1, the start of the line is relative to HSB.
VSBHO, VS Begin Horizontal Position Odd, Address 0x32[7]
The VSBHO and VSBHE bits select the position within a line at
which the VS pin (not the bit in the AV code) becomes active.
Some follow-on chips require the VS pin to change state only
when HS is high or low.
SQPE, Square Pixel Mode, Address 0x01[2]
The SQPE bit allows the user to select the square pixel mode.
This mode is not suitable for poor time-based video sources.
This mode is recommended for professional applications only
and should not be used with VCR or tuner sources.
When VSBHO is 0 (default), the VS pin goes high in the middle
of a line of video (odd field).
When VSBHO is 1, the VS pin changes state at the start of a line
(odd field).
Setting SQPE to 1 enables square pixel mode. The LLC for
NTSC is 24.5454 MHz and 29.5 MHz for PAL. The crystal
frequency does not change.
VSBHE, VS Begin Horizontal Position Even, Address 0x32[6]
VS/FIELD, Address 0x58[0]
The VSBHO and VSBHE bits select the position within a line at
which the VS pin (not the bit in the AV code) becomes active.
Some follow-on chips require the VS pin to only change state
when HS is high or low.
This feature is used for the 48-lead LQFP, 40-lead LFCSP, and
32-lead LFCSP only. The polarity of this bit determines what
signal appears on the VS/FIELD pin.
When VSBHE is 0 (default), the VS pin goes high in the middle
of a line of video (even field).
When this bit is set to 0 (default), the FIELD signal is output.
When this bit is set to 1, the VSYNC signal is output.
The 64-lead LQFP has dedicated FIELD and VSYNC pins.
When VSBHE is 1, the VS pin changes state at the start of a line
(even field).
ADV encoder-compatible signals via the NEWAVMODE
register follow:
VSEHO, VS End Horizontal Position Odd, Address 0x33[7]
The VSEHO and VSEHE bits select the position within a line at
which the VS pin (not the bit in the AV code) becomes active.
Some follow-on chips require the VS pin to change state only
when HS is high or low.
•
•
•
•
PVS, PF
HVSTIM
VSBHO, VSBHE
VSEHO, VSEHE
When VSEHO is 0 (default), the VS pin goes low (inactive) in
the middle of a line of video (odd field).
For NTSC control,
•
•
•
NVBEGDELO, NVBEGDELE, NVBEGSIGN, NVBEG[4:0]
NVENDDELO, NVENDDELE, NVENDSIGN, NVEND[4:0]
NFTOGDELO, NFTOGDELE, NFTOGSIGN, NFTOG[4:0]
When VSEHO is 1, the VS pin changes state at the start of a line
(odd field).
VSEHE, VS End Horizontal Position Even, Address 0x33[6]
For PAL control,
The VSEHO and VSEHE bits select the position within a line at
which the VS pin (not the bit in the AV code) becomes active.
Some follow-on chips require the VS pin to change state only
when HS is high or low.
•
•
•
PVBEGDELO, PVBEGDELE, PVBEGSIGN, PVBEG[4:0]
PVENDDELO, PVENDDELE, PVENDSIGN, PVEND[4:0]
PFTOGDELO, PFTOGDELE, PFTOGSIGN, PFTOG[4:0]
NEWAVMODE, New AV Mode, Address 0x31[4]
When VSEHE is 0 (default), the VS pin goes low (inactive) in
the middle of a line of video (even field).
When NEWAVMODE is 0, EAV/SAV codes are generated to
suit Analog Devices encoders. No adjustments are possible.
When VSEHE is 1, the VS pin changes state at the start of a line
(even field).
Setting NEWAVMODE to 1 (default) enables the manual position
of the VSYNC, FIELD, and AV codes using Register 0x32 to
Register 0x33 and Register 0xE5 to Register 0xEA. Default register
settings are CCIR656 compliant; see Figure 36 for NTSC and
Figure 41 for PAL. For recommended manual user settings, see
Table 65 and Figure 37 for NTSC and Table 66 and Figure 42 for PAL.
PVS, Polarity VS, Address 0x37[5]
The polarity of the VS pin can be inverted using the PVS bit.
When PVS is 0 (default), VS is active high.
When PVS is 1, VS is active low.
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