ADV7123
Parameter
Min
Typ
Max
Unit
Total Harmonic Distortion
fCLK = ꢀ0 MHz; fOUT = 1.00 MHz
TA = 2ꢀ°C
66
6ꢀ
64
64
ꢀꢀ
dBc
dBc
dBc
dBc
dBc
TMIN to TMAX
fCLK = ꢀ0 MHz; fOUT = 2.00 MHz
fCLK = 100 MHz; fOUT = 2.00 MHz
fCLK = 140 MHz; fOUT = 2.00 MHz
DAC PERFORMANCE
Glitch Impulse
DAC-to-DAC Crosstalk3
Data Feedthrough4, ꢀ
Clock Feedthrough4, ꢀ
10
23
22
33
pV-sec
dB
dB
dB
1 These maximum/minimum specifications are guaranteed by characterization over the 3.0 V to 3.6 V range.
2 Note that the ADV7123 exhibits high performance when operating with an internal voltage reference, VREF
.
3 DAC-to-DAC crosstalk is measured by holding one DAC high while the other two are making low-to-high and high-to-low transitions.
4 Clock and data feedthrough is a function of the amount of overshoot and undershoot on the digital inputs. Glitch impulse includes clock and data feedthrough.
ꢀ TTL input values are 0 V to 3 V, with input rise/fall times of −3 ns, measured at the 10% and 90% points. Timing reference points are ꢀ0% for inputs and outputs.
5 V TIMING SPECIFICATIONS
VAA = 5 V 5ꢀ,1 VREF = 1.235 V, RSET = 560 Ω, CL = 10 pF. All specifications TMIN to TMAX,2 unless otherwise noted, TJ MAX = 110°C.
Table 5.
Parameter3
Symbol
Min
Typ
Max
Unit
Conditions
ANALOG OUTPUTS
Analog Output Delay
Analog Output Rise/Fall Time4
Analog Output Transition Timeꢀ
Analog Output Skew6
CLOCK CONTROL
t6
t7
t8
t9
ꢀ.ꢀ
1.0
1ꢀ
1
ns
ns
ns
ns
2
CLOCK Frequency7
fCLK
0.ꢀ
ꢀ0
MHz
ꢀ0 MHz grade
140 MHz grade
240 MHz grade
0.ꢀ
0.ꢀ
140
240
MHz
MHz
Data and Control Setup
Data and Control Hold
CLOCK Period
t1
t2
t3
t4
tꢀ
t4
tꢀ
t4
tꢀ
tPD
t10
0.ꢀ
1.ꢀ
ns
ns
ns
ns
ns
ns
ns
ns
4.17
1.87ꢀ
1.87ꢀ
2.8ꢀ
2.8ꢀ
8.0
CLOCK Pulse Width High
CLOCK Pulse Width Low
CLOCK Pulse Width High
CLOCK Pulse Width Low
CLOCK Pulse Width High
CLOCK Pulse Width Low
Pipeline Delay6
fCLK_MAX = 240 MHz
fCLK_MAX = 240 MHz
fCLK_MAX = 140 MHz
fCLK_MAX = 140 MHz
fCLK_MAX = ꢀ0 MHz
fCLK_MAX = ꢀ0 MHz
8.0
1.0
ns
1.0
2
1.0
10
Clock cycles
ns
PSAVE Up Time6
1 These maximum and minimum specifications are guaranteed over this range.
2 Temperature range: TMIN to TMAX: −40°C to +8ꢀ°C at ꢀ0 MHz and 140 MHz, 0°C to 70°C at 240 MHz.
3 Timing specifications are measured with input levels of 3.0 V (VIH) and 0 V (VIL) 0 for both ꢀ V and 3.3 V supplies.
4 Rise time was measured from the 10% to 90% point of zero to full-scale transition, fall time from the 90% to 10% point of a full-scale transition.
ꢀ Measured from ꢀ0% point of full-scale transition to 2% of final value.
6 Guaranteed by characterization.
7 fCLK maximum specification production tested at 12ꢀ MHz; ꢀ V limits specified here are guaranteed by characterization.
Rev. D | Page 7 of 24
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