ADV7123
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
48 47 46 45 44 43 42 41 40 39 38 37
1
36
35
34
33
32
31
30
29
28
27
26
25
V
G0
REF
PIN 1
INDICATOR
2
3
G1
G2
COMP
IOR
4
G3
IOR
5
G4
IOG
6
ADV7123
TOP VIEW
(Not to Scale)
G5
IOG
G6
7
V
V
AA
AA
8
G7
G8
9
IOB
G9
10
11
12
IOB
BLANK
SYNC
GND
GND
13 14 15 16 17 18 19 20 21 22 23 24
Figure 3. Pin Configuration
Table 8. Pin Function Descriptions
Pin No.
Mnemonic
Description
1 to 10,
14 to 23,
39 to 48
G0 to G9,
B0 to B9,
R0 to R9
Red, Green, and Blue Pixel Data Inputs (TTL Compatible). Pixel data is latched on the rising edge of CLOCK. R0,
G0, and B0 are the least significant data bits. Unused pixel data inputs should be connected to either the
regular printed circuit board (PCB) power or ground plane.
11
BLANK
Composite Blank Control Input (TTL Compatible). A Logic 0 on this control input drives the analog outputs,
IOR, IOB, and IOG, to the blanking level. The BLANK signal is latched on the rising edge of CLOCK. While
BLANK is a Logic 0, the R0 to R9, G0 to G9, and B0 to B9 pixel inputs are ignored.
12
SYNC
Composite Sync Control Input (TTL Compatible). A Logic 0 on the SYNC input switches off a 40 IRE current
source. This is internally connected to the IOG analog output. SYNC does not override any other control or
data input; therefore, it should only be asserted during the blanking interval. SYNC is latched on the rising
edge of CLOCK. If sync information is not required on the green channel, the SYNC input should be tied to
Logic 0.
13, 29, 30
24
VAA
CLOCK
Analog Power Supply (ꢀ V ꢀ%). All VAA pins on the ADV7123 must be connected.
Clock Input (TTL Compatible). The rising edge of CLOCK latches the R0 to R9, G0 to G9, B0 to B9, SYNC, and
BLANK pixel and control inputs. It is typically the pixel clock rate of the video system. CLOCK should be driven
by a dedicated TTL buffer.
2ꢀ, 26
GND
Ground. All GND pins must be connected.
27, 31, 33
IOB, IOG, IOR
Differential Red, Green, and Blue Current Outputs (High Impedance Current Sources). These RGB video
outputs are specified to directly drive RS-343A and RS-170 video levels into a doubly terminated 7ꢀ Ω load. If
the complementary outputs are not required, these outputs should be tied to ground.
28, 32, 34
IOB, IOG, IOR
Red, Green, and Blue Current Outputs. These high impedance current sources are capable of directly driving a
doubly terminated 7ꢀ Ω coaxial cable. All three current outputs should have similar output loads whether or
not they are all being used.
3ꢀ
36
COMP
VREF
Compensation Pin. This is a compensation pin for the internal reference amplifier. A 0.1 μF ceramic capacitor
must be connected between COMP and VAA.
Voltage Reference Input for DACs or Voltage Reference Output (1.23ꢀ V).
Rev. D | Page 10 of 24
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