ADuM1410/ADuM1411/ADuM1412
Parameter
10 Mbps (BRW Grade Only)
Symbol Min
Typ
Max Unit
Test Conditions
VDD1 Supply Current
5 V/3 V Operation
3 V/5 V Operation
VDD2 Supply Current
5 V/3 V Operation
3 V/5 V Operation
IDD1 (10)
4.6
2.6
6.5 mA
3.8 mA
5 MHz logic signal frequency
5 MHz logic signal frequency
IDD2 (10)
2.6
4.6
3.8 mA
6.5 mA
5 MHz logic signal frequency
5 MHz logic signal frequency
For All Models
Input Currents
IIA, IIB, IIC, −10
+0.01
+10 μA
0 ≤ VIA,VIB, VIC,VID ≤ VDD1 or VDD2,
IID, ICTRL1
ICTRL2
IDISABLE
VIH
,
0 ≤ VCTRL1,VCTRL2 ≤ VDD1 or VDD2
VDISABLE ≤ VDD1
,
,
Logic High Input Threshold
5 V/3 V Operation
3 V/5 V Operation
2.0
1.6
V
V
Logic Low Input Threshold
5 V/3 V Operation
3 V/5 V Operation
VIL
0.8
0.4
V
V
V
V
V
V
V
Logic High Output Voltages
VOAH, VOBH, VDD1, VDD2 − 0.1 VDD1, VDD2
VOCH, VODH
IOx = −20 μA, VIx = VIxH
IOx = −4 mA, VIx = VIxH
IOx = 20 μA, VIx = VIxL
IOx = 400 μA, VIx = VIxL
IOx = 4 mA, VIx = VIxL
VDD1, VDD2 − 0.4 VDD1, VDD − 0.2
Logic Low Output Voltages
VOAL, VOBL
VOCL, VODL
,
0.0
0.04
0.2
0.1
0.1
0.4
SWITCHING SPECIFICATIONS
ADuM1411ARW and ADuM1412ARW
Minimum Pulse Width3
PW
1000 ns
Mbps
100 ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
Maximum Data Rate4
1
25
Propagation Delay5
tPHL, tPLH
PWD
tPSK
70
5
Pulse Width Distortion, |tPLH − tPHL
Propagation Delay Skew6
Channel-to-Channel Matching7
ADuM141xBRW
|
40
50
50
ns
ns
ns
tPSKCD/OD
Minimum Pulse Width3
Maximum Data Rate4
PW
100 ns
Mbps
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
10
25
Propagation Delay5
tPHL, tPLH
PWD
35
5
60
5
5
Pulse Width Distortion, |tPLH − tPHL
Change vs. Temperature
Propagation Delay Skew6
Channel-to-Channel Matching,
Codirectional Channels7
|
ns
ps/°C
ns
ns
tPSK
tPSKCD
30
5
Channel-to-Channel Matching,
tPSKOD
6
ns
CL = 15 pF, CMOS signal levels
Opposing-Directional Channels7
For All Models
Output Rise/Fall Time (10% to 90%)
5 V/3 V Operation
3 V/5 V Operation
Common-Mode Transient Immunity
at Logic High Output8
Common-Mode Transient Immunity
at Logic Low Output8
tR/tf
CL = 15 pF, CMOS signal levels
2.5
2.5
35
ns
ns
kV/μs
|CMH|
|CML|
fr
25
25
VIx = VDD1/VDD2, VCM = 1000 V,
transient magnitude = 800 V
VIx = 0 V, VCM = 1000 V, transient
magnitude = 800 V
35
kV/μs
Refresh Rate
5 V/3 V Operation
3 V/5 V Operation
Input Enable Time9
1.2
1.1
2.0
Mbps
Mbps
μs
tENABLE
VIA, VIB, VIC, VID = 0 or VDD1
Rev. E | Page 8 of 20
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