ADuM1410/ADuM1411/ADuM1412
ELECTRICAL CHARACTERISTICS—3 V OPERATION
2.7 V ≤ VDD1 ≤ 3.6 V, 2.7 V ≤ VDD2 ≤ 3.6 V; all min/max specifications apply over the entire recommended operation range, unless
otherwise noted; all typical specifications are at TA = 25°C, VDD1 = VDD2 = 3.0 V. 1
Table 2.
Parameter
Symbol
Min
Typ Max Unit
Test Conditions
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent
IDDI (Q)
0.25 0.38 mA
0.19 0.33 mA
Output Supply Current per Channel, Quiescent IDDO (Q)
ADuM1410, Total Supply Current, Four Channels2
DC to 2 Mbps
VDD1 Supply Current
VDD2 Supply Current
IDD1 (Q)
IDD2 (Q)
1.2
0.8
1.6 mA
1.0 mA
DC to 1 MHz logic signal frequency
DC to 1 MHz logic signal frequency
10 Mbps (BRW Grade Only)
VDD1 Supply Current
VDD2 Supply Current
IDD1 (10)
IDD2 (10)
4.5
1.4
6.5 mA
1.8 mA
5 MHz logic signal frequency
5 MHz logic signal frequency
ADuM1411, Total Supply Current, Four Channels2
DC to 2 Mbps
VDD1 Supply Current
VDD2 Supply Current
IDD1 (Q)
IDD2 (Q)
1.0
0.9
1.9 mA
1.7 mA
DC to 1 MHz logic signal frequency
DC to 1 MHz logic signal frequency
10 Mbps (BRW Grade Only)
VDD1 Supply Current
VDD2 Supply Current
IDD1 (10)
IDD2 (10)
3.1
2.1
4.5 mA
3.0 mA
5 MHz logic signal frequency
5 MHz logic signal frequency
ADuM1412, Total Supply Current, Four Channels2
DC to 2 Mbps
VDD1 or VDD2 Supply Current
10 Mbps (BRW Grade Only)
VDD1 or VDD2 Supply Current
For All Models
IDD1 (Q), IDD2 (Q)
IDD1 (10), IDD2 (10)
IIA, IIB, IIC,
1.0
2.6
1.8 mA
3.8 mA
DC to 1 MHz logic signal frequency
5 MHz logic signal frequency
Input Currents
−10
1.6
+0.01 +10 μA
0 ≤ VIA,VIB, VIC,VID ≤ VDD1 or VDD2,
IID, ICTRL1
,
0 ≤ VCTRL1,VCTRL2 ≤ VDD1 or VDD2
,
ICTRL2, IDISABLE
VIH
VIL
VDISABLE ≤ VDD1
Logic High Input Threshold
Logic Low Input Threshold
Logic High Output Voltages
V
0.4
0.1
V
V
V
V
V
V
VOAH, VOBH
,
VDD1, VDD2 − 0.1 3.0
VDD1, VDD2 − 0.4 2.8
0.0
IOx = −20 μA, VIx = VIxH
IOx = −4 mA, VIx = VIxH
IOx = 20 μA, VIx = VIxL
IOx = 400 μA, VIx = VIxL
IOx = 4 mA, VIx = VIxL
VOCH, VODH
Logic Low Output Voltages
VOAL, VOBL
,
VOCL, VODL
0.04 0.1
0.2
0.4
SWITCHING SPECIFICATIONS
ADuM1411ARW and ADuM1412ARW
Minimum Pulse Width3
PW
1000 ns
Mbps
100 ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
Maximum Data Rate4
1
20
Propagation Delay5
tPHL, tPLH
PWD
tPSK
75
5
Pulse Width Distortion, |tPLH − tPHL
Propagation Delay Skew6
Channel-to-Channel Matching7
ADuM141xBRW
|
40
50
50
ns
ns
ns
tPSKCD/OD
Minimum Pulse Width3
Maximum Data Rate4
Propagation Delay5
PW
100 ns
Mbps
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
10
20
tPHL, tPLH
40
60
Rev. E | Page 5 of 20
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