ADuM1410/ADuM1411/ADuM1412
Parameter
Symbol
Min
Typ
Max Unit
Test Conditions
ADuM141xBRW
Minimum Pulse Width3
PW
100
ns
Mbps
ns
ns
ps/°C
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
Maximum Data Rate4
10
20
Propagation Delay5
tPHL, tPLH
PWD
30
5
50
5
5
Pulse Width Distortion, |tPLH − tPHL
Change vs. Temperature
Propagation Delay Skew6
Channel-to-Channel Matching,
Codirectional Channels7
|
tPSK
tPSKCD
30
5
ns
Channel-to-Channel Matching,
tPSKOD
6
ns
CL = 15 pF, CMOS signal levels
Opposing-Directional Channels7
For All Models
Output Rise/Fall Time (10% to 90%)
Common-Mode Transient Immunity |CMH|
at Logic High Output8
Common-Mode Transient Immunity |CML|
at Logic Low Output8
tR/tF
2.5
35
ns
kV/μs
CL = 15 pF, CMOS signal levels
VIx = VDD1/VDD2, VCM = 1000 V,
transient magnitude = 800 V
VIx = 0 V, VCM = 1000 V,
transient magnitude = 800 V
25
25
35
kV/μs
Refresh Rate
Input Enable Time9
Input Disable Time9
Input Dynamic Supply Current per
Channel10
Output Dynamic Supply Current per IDDO (D)
Channel10
fr
1.2
Mbps
μs
μs
tENABLE
tDISABLE
IDDI (D)
2.0
5.0
VIA, VIB, VIC, VID, = 0 or VDD1
VIA, VIB, VIC, VID, = 0 or VDD1
0.12
0.04
mA/Mbps
mA/Mbps
1 All voltages are relative to their respective ground.
2 The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section.
See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through
Figure 15 for total VDD1 and VDD2 supply currents as a function of data rate for ADuM1410/ADuM1411/ADuM1412 channel configurations.
3 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
4 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
5 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
6 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load
within the recommended operating conditions.
7 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
8 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate
that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
9 Input enable time is the duration from when VDISABLE is set low until the output states are guaranteed to match the input states in the absence of any input data logic
transitions. If an input data logic transition within a given channel does occur within this time interval, the output of that channel reaches the correct state within the
much shorter duration as determined by the propagation delay specifications within this data sheet. Input disable time is the duration from when VDISABLE is set high
until the output states are guaranteed to reach their programmed output levels, as determined by the CTRL logic state (See Table 10).
10 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information
on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current
for a given data rate.
Rev. E | Page 4 of 20
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