ADuC7019/20/21/22/24/25/26/27/28/29
Data Sheet
For example, do not power components on the analog side (as
seen in Figure 91b) with IOVDD because that forces return
currents from IOVDD to flow through AGND. Avoid digital
currents flowing under analog circuitry, which can occur if a
noisy digital chip is placed on the left half of the board (shown
in Figure 91c). If possible, avoid large discontinuities in the
ground plane(s) such as those formed by a long trace on the same
layer because they force return signals to travel a longer path.
In addition, make all connections to the ground plane directly,
with little or no trace separating the pin from its via to ground.
GROUNDING AND BOARD LAYOUT
RECOMMENDATIONS
As with all high resolution data converters, special attention
must be paid to grounding and PC board layout of the
ADuC7019/20/21/22/24/25/26/27/28/29-based designs to
achieve optimum performance from the ADCs and DAC.
Although the parts have separate pins for analog and digital
ground (AGND and IOGND), the user must not tie these to
two separate ground planes unless the two ground planes are
connected very close to the part. This is illustrated in the
simplified example shown in Figure 91a. In systems where
digital and analog ground planes are connected together
somewhere else (at the system power supply, for example), the
planes cannot be reconnected near the part because a ground
loop results. In these cases, tie all the ADuC7019/20/21/
22/24/25/26/27/28/29 AGND and IOGND pins to the analog
ground plane, as illustrated in Figure 91b. In systems with only
one ground plane, ensure that the digital and analog components
are physically separated onto separate halves of the board so
that digital return currents do not flow near analog circuitry
(and vice versa).
When connecting fast logic signals (rise/fall time < 5 ns) to any of
the ADuC7019/20/21/22/24/25/26/27/28/29 digital inputs, add a
series resistor to each relevant line to keep rise and fall times
longer than 5 ns at the part’s input pins. A value of 100 Ω or
200 Ω is usually sufficient to prevent high speed signals from
coupling capacitively into the part and affecting the accuracy
of ADC conversions.
CLOCK OSCILLATOR
The clock source for the ADuC7019/20/21/22/24/25/26/27/28/29
can be generated by the internal PLL or by an external clock
input. To use the internal PLL, connect a 32.768 kHz parallel
resonant crystal between XCLKI and XCLKO, and connect a
capacitor from each pin to ground as shown in Figure 92. The
crystal allows the PLL to lock correctly to give a frequency of
41.78 MHz. If no external crystal is present, the internal
oscillator is used to give a typical frequency of 41.78 MHz 3%.
The ADuC7019/20/21/22/24/25/26/27/28/29 can then be
placed between the digital and analog sections, as illustrated in
Figure 91c.
PLACE ANALOG
COMPONENTS HERE
PLACE DIGITAL
COMPONENTS HERE
ADuC7026
a.
XCLKI
45
12pF
AGND
DGND
32.768kHz
TO
INTERNAL
PLL
44
12pF
XCLKO
Figure 92. External Parallel Resonant Crystal Connections
PLACE ANALOG
COMPONENTS
HERE
PLACE DIGITAL
To use an external source clock input instead of the PLL (see
Figure 93), Bit 1 and Bit 0 of PLLCON must be modified.The
external clock uses P0.7 and XCLK.
COMPONENTS HERE
b.
AGND
DGND
ADuC7026
XCLKO
XCLKI
EXTERNAL
CLOCK
SOURCE
TO
PLACE ANALOG
COMPONENTS HERE
PLACE DIGITAL
COMPONENTS HERE
FREQUENCY
DIVIDER
c.
XCLK
Figure 93. Connecting an External Clock Source
DGND
Using an external clock source, the ADuC7019/20/21/22/24/
25/26/27/28/29-specified operational clock speed range is
50 kHz to 44 MHz 1%, which ensures correct operation of
the analog peripherals and Flash/EE.
Figure 91. System Grounding Schemes
In all of these scenarios, and in more complicated real-life
applications, the user should pay particular attention to the flow
of current from the supplies and back to ground. Make sure the
return paths for all currents are as close as possible to the paths
the currents took to reach their destinations.
Rev. F | Page 94 of 104
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