Data Sheet
ADuC7019/20/21/22/24/25/26/27/28/29
HARDWARE DESIGN CONSIDERATIONS
Finally, note that the analog and digital ground pins on the
ADuC7019/20/21/22/24/25/26/27/28/29 must be referenced to
the same system ground reference point at all times.
POWER SUPPLIES
The ADuC7019/20/21/22/24/25/26/27/28/29 operational power
supply voltage range is 2.7 V to 3.6 V. Separate analog and
digital power supply pins (AVDD and IOVDD, respectively) allow
AVDD to be kept relatively free of noisy digital signals often
present on the system IOVDD line. In this mode, the part can
also operate with split supplies; that is, it can use different
voltage levels for each supply. For example, the system can
be designed to operate with an IOVDD voltage level of 3.3 V
whereas the AVDD level can be at 3 V or vice versa. A typical
split supply configuration is shown in Figure 87.
IOVDD Supply Sensitivity
The IOVDD supply is sensitive to high frequency noise because it
is the supply source for the internal oscillator and PLL circuits.
When the internal PLL loses lock, the clock source is removed
by a gating circuit from the CPU, and the ARM7TDMI core
stops executing code until the PLL regains lock. This feature
ensures that no flash interface timings or ARM7TDMI timings
are violated.
DIGITAL
SUPPLY
ANALOG
SUPPLY
Typically, frequency noise greater than 50 kHz and 50 mV p-p
on top of the supply causes the core to stop working.
+
–
+
–
10µF
10µF
If decoupling values recommended in the Power Supplies
section do not sufficiently dampen all noise sources below
50 mV on IOVDD, a filter such as the one shown in Figure 89
is recommended.
ADuC7026
73
74
75
AV
DD
26
54
IOV
DD
DACV
DD
0.1µF
0.1µF
8
GND
REF
70
71
67
DACGND
AGND
ADuC7026
1µH
25
53
26
IOGND
IOV
DD
REFGND
10µF
54
DIGITAL
SUPPLY
+
–
Figure 87. External Dual Supply Connections
0.1µF
As an alternative to providing two separate power supplies, the
user can reduce noise on AVDD by placing a small series resistor
and/or ferrite bead between AVDD and IOVDD and then decoupling
AVDD separately to ground. An example of this configuration is
shown in Figure 88. With this configuration, other analog circuitry
(such as op amps and voltage reference) can be powered from
the AVDD supply line as well.
25
53
IOGND
Figure 89. Recommended IOVDD Supply Filter
Linear Voltage Regulator
Each ADuC7019/20/21/22/24/25/26/27/28/29 requires a single
3.3 V supply, but the core logic requires a 2.6 V supply. An on-
chip linear regulator generates the 2.6 V from IOVDD for the
core logic. The LVDD pin is the 2.6 V supply for the core logic.
An external compensation capacitor of 0.47 µF must be
connected between LVDD and DGND (as close as possible to
these pins) to act as a tank of charge as shown in Figure 90.
BEAD
DIGITAL SUPPLY
1.6Ω
10µF
10µF
+
–
ADuC7026
73
AV
DD
74
75
26
54
IOV
DD
DACV
DD
0.1µF
0.1µF
8
GND
REF
ADuC7026
70
71
67
DACGND
AGND
25
53
27
LV
DD
IOGND
REFGND
0.47mF
28
DGND
Figure 88. External Single Supply Connections
Note that in both Figure 87 and Figure 88, a large value (10 µF)
reservoir capacitor sits on IOVDD, and a separate 10 µF capacitor
sits on AVDD. In addition, local small-value (0.1 µF) capacitors are
located at each AVDD and IOVDD pin of the chip. As per standard
design practice, be sure to include all of these capacitors and ensure
that the smaller capacitors are close to each AVDD pin with trace
lengths as short as possible. Connect the ground terminal of
each of these capacitors directly to the underlying ground plane.
Figure 90. Voltage Regulator Connections
The LVDD pin should not be used for any other chip. It is also
recommended to use excellent power supply decoupling on
IOVDD to help improve line regulation performance of the on-
chip voltage regulator.
Rev. F | Page 93 of 104
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