Data Sheet
ADuC7019/20/21/22/24/25/26/27/28/29
3.3V
POWER-ON RESET OPERATION
IOV
DD
An internal power-on reset (POR) is implemented on the
ADuC7019/20/21/22/24/25/26/27/28/29. For LVDD below 2.35 V
typical, the internal POR holds the part in reset. As LVDD rises
above 2.35 V, an internal timer times out for, typically, 128 ms
before the part is released from reset. The user must ensure that
the power supply IOVDD reaches a stable 2.7 V minimum level
by this time. Likewise, on power-down, the internal POR holds
the part in reset until LVDD drops below 2.35 V.
2.6V
2.35V TYP
2.35V TYP
LV
DD
128ms TYP
POR
Figure 94 illustrates the operation of the internal POR in detail.
0.12ms TYP
TYPICAL SYSTEM CONFIGURATION
MRST
A typical ADuC7020 configuration is shown in Figure 95. It
summarizes some of the hardware considerations discussed in
the previous sections. The bottom of the CSP package has an
exposed pad that must be soldered to a metal plate on the board
for mechanical reasons. The metal plate of the board can be
connected to ground.
Figure 94. Internal Power-On Reset Operation
+
–
10Ω
0.01µF
RS232 INTERFACE*
0.47µF
AV
DD
STANDARD D-TYPE
SERIAL COMMS
40 39 38 37 36 35 34 33 32 31
DV
DD
ADM3202
CONNECTOR TO
PC HOST
1
2
30
29
28
27
26
25
24
23
22
21
1
2
3
4
5
6
7
8
C1+
V
16
CC
1
2
3
4
5
6
7
8
9
V+
GND 15
3
GND
REF
C1–
C2+
C2–
V–
T1
14
13
12
11
10
9
OUT
4
DAC0
R1
IN
5
R1
OUT
ADuC7020
6
XCLKI
T1
T2
IN
IN
7
XCLKO
T2
OUT
8
TMS
TDI
32.768kHz
R2
R2
OUT
IN
9
10
P0.0
1kΩ
DV
DD
11 12 13 14 15 16 17 18 19 20
* EXTERNAL UART TRANSCEIVER INTEGRATED IN SYSTEM OR AS
PART OF AN EXTERNAL DONGLE AS DESCRIBED IN uC006.
DV
DD
1kΩ
0.47µF
DV
DD
DV
DD
AV
1
2
3
DD
DV
DD
ADP3333-3.3
TRST
1.5Ω
OUT IN
4
5
6
7
8
9
TDI
270Ω
GND SD
TMS
TCK
10µF
10µF
0.1µF
10
11
12
13
14
15
16
17
18
19
20
TDO
NOT CONNECTED IN THIS EXAMPLE
Figure 95. Typical System Configuration
Rev. F | Page 95 of 104
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