ADSP-BF531/ADSP-BF532/ADSP-BF533
External Port Bus Request and Grant Cycle Timing
and
describe external port bus request and
bus grant operations.
Table 26. External Port Bus Request and Grant Cycle Timing
V
DDEXT
= 1.8 V
V
DDEXT
= 1.8 V
V
DDEXT
= 2.5 V/3.3 V
LQFP/PBGA Packages CSP_BGA Package
All Packages
Min
Max
Min
Max
Min
Max
Unit
4.6
1.0
4.5
4.5
6.0
6.0
6.0
6.0
4.6
1.0
4.5
4.5
5.5
4.6
5.5
4.6
4.6
0.0
4.5
4.5
3.6
3.6
3.6
3.6
ns
ns
ns
ns
ns
ns
ns
ns
Parameter
Timing Requirements
t
BS
BR Asserted to CLKOUT High Setup
t
BH
CLKOUT High to BR Deasserted Hold Time
Switching Characteristics
t
SD
CLKOUT Low to AMSx, Address, and ARE/AWE Disable
t
SE
CLKOUT Low to AMSx, Address, and ARE/AWE Enable
t
DBG
CLKOUT High to BG High Setup
t
EBG
CLKOUT High to BG Deasserted Hold Time
t
DBH
CLKOUT High to BGH High Setup
t
EBH
CLKOUT High to BGH Deasserted Hold Time
CLKOUT
t
BS
BR
t
BH
t
SD
AMSx
t
SE
t
SD
ADDR 19-1
ABE1-0
t
SE
t
SD
AWE
ARE
t
SE
t
DBG
BG
t
EBG
t
DBH
BGH
t
EBH
Figure 16. External Port Bus Request and Grant Cycle Timing
Rev. H
| Page 32 of 64 | January 2011
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